cy7c1380d-250bzxi Cypress Semiconductor Corporation., cy7c1380d-250bzxi Datasheet
cy7c1380d-250bzxi
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cy7c1380d-250bzxi Summary of contents
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... Separate processor and controller address strobes • Synchronous self-timed write • Asynchronous output enable • Single cycle chip deselect • CY7C1380D/CY7C1382D available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA package. CY7C1380F/CY7C1382F available in Pb-free and non Pb-free 119-ball BGA package • ...
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... Logic Block Diagram – CY7C1380D/CY7C1380F A0, A1, A ADDRESS REGISTER MODE ADV CLK ADSC ADSP DQ DQP BYTE BW D WRITE REGISTER DQ DQP BYTE C WRITE REGISTER DQ DQP BYTE BW B WRITE REGISTER DQ DQP BYTE A WRITE REGISTER BWE GW ENABLE CE 1 REGISTER ...
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... DDQ V 21 SSQ SSQ V 27 DDQ DQP D 30 Document #: 38-05543 Rev. *E CY7C1380D, CY7C1380F CY7C1382D, CY7C1382F DQP DDQ 4 DDQ SSQ 5 SSQ ...
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... BWE DQP MODE NC/36M A TMS TDI TCK TDO CY7C1380D, CY7C1380F CY7C1382D, CY7C1382F DDQ A NC/576M A NC/1G DQP DDQ DDQ DQ ...
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... B DDQ DDQ DDQ DDQ N DQP DDQ P NC NC/72M A R MODE NC/36M A Document #: 38-05543 Rev. *E CY7C1380D (512K x 36 BWE CLK ...
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... CE to select or deselect the device select or deselect the device sampled only when a new external address deasserted HIGH. 1 are placed in a tri-state condition. X CY7C1380D, CY7C1380F CY7C1382D, CY7C1382F [ and CE are sampled active. A1 and BWE HIGH. CE ...
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... ADSP is asserted LOW, and ( CY7C1380D, CY7C1380F CY7C1382D, CY7C1382F or left DD . This pin is not available This pin is not available on DD are all asserted active, and (3) the write are all asserted active. The address ...
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... A synchronous self-timed write mechanism has been provided to simplify the write operations. The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F is a common IO device, the output enable (OE) must be deserted HIGH before presenting data to the DQs inputs. Doing so will tri-state the output drivers safety precaution, DQs are automatically tri-stated whenever a write cycle is detected, regardless of the state of OE ...
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... OE is asynchronous and is not sampled with the clock rise masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW) . Document #: 38-05543 Rev. *E CY7C1380D, CY7C1380F CY7C1382D, CY7C1382F CE ...
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... A A Write Byte B – (DQ and DQP ) B B Write Bytes B, A Write All Bytes Write All Bytes Note: 9. Table only lists a partial listing of the byte write combinations. Any combination of BW Document #: 38-05543 Rev. *E CY7C1380D, CY7C1380F CY7C1382D, CY7C1382F GW BWE ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1380D/CY7C1382D incorporates a serial boundary scan test access port (TAP).This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V IO logic levels. The CY7C1380D/CY7C1382D contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register ...
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... IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The boundary scan register has a special bit located at bit #85 (for 119-BGA package) or bit #89 (for 165-fBGA package). CY7C1380D, CY7C1380F CY7C1382D, CY7C1382F ). The SRAM clock input might not be CH ...
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... Do not use these instructions CYC TL t TMSS t TMSH t TDIS t TDIH t TDOV t TDOX DON’T CARE UNDEFINED [10, 11] Over the Operating Range Description /t = 1ns CY7C1380D, CY7C1380F CY7C1382D, CY7C1382F Min. Max. Unit MHz ...
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... V = 3.3V OH DDQ V = 2.5V DDQ 3.3V OL DDQ V = 2.5V DDQ I = 100 µ 3.3V OL DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ GND < V < DDQ CY7C1380D, CY7C1380F CY7C1382D, CY7C1382F to 2.5V SS 1.25V 50Ω Ω 20pF O Min. Max. Unit 2.4 V 2.0 V 2.9 V 2.1 V 0.4 V 0.4 V 0.2 V 0 –0.3 0.8 V – ...
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... Bit Size (x36 Description CY7C1380D, CY7C1380F CY7C1382D, CY7C1382F Description Describes the version number. Reserved for internal use. Defines the memory type and architecture. Defines the memory type and architecture. Defines the width and density. Allows unique identification of SRAM vendor ...
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... Notes: 14. Balls which are NC (No Connect) are pre-set LOW. 15. Bit pre-set HIGH. Document #: 38-05543 Rev. *E CY7C1380D, CY7C1380F CY7C1382D, CY7C1382F [14, 15] Ball ID Bit # Ball ...
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... M10 19 L10 20 K10 21 J10 H10 24 G11 25 F11 26 E11 27 D11 28 G10 29 F10 30 E10 Note: 16. Bit pre-set HIGH. Document #: 38-05543 Rev. *E CY7C1380D, CY7C1380F CY7C1382D, CY7C1382F [14, 16] Bit # Ball ID 31 D10 32 C11 33 A11 34 B11 35 A10 36 B10 C10 ...
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... /2), undershoot: V (AC) > –2V (pulse width less than t CYC IL (min.) within 200 ms. During this time V < V and CY7C1380D, CY7C1380F CY7C1382D, CY7C1382F + 0.5V DD Ambient Temperature DDQ 0°C to +70°C 3.3V –5%/+10% 2.5V – Min. Max. 3.135 3 ...
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... DDQ GND 351Ω INCLUDING JIG AND (b) SCOPE R = 1667Ω 2.5V V DDQ GND 1538Ω INCLUDING JIG AND SCOPE (b) CY7C1380D, CY7C1380F CY7C1382D, CY7C1382F 119 BGA 165 FBGA Package Package Unit 119 BGA 165 FBGA Package Package Unit 23 ...
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... V AC Test Loads and Waveforms on page and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ CY7C1380D, CY7C1380F CY7C1382D, CY7C1382F 200 MHz 167 MHz Min. Max. Min. Max. ...
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... CO t OEHZ t OELZ t DOH Q(A2 BURST READ DON’T CARE UNDEFINED is HIGH and CE is LOW. When CE is HIGH CY7C1380D, CY7C1380F CY7C1382D, CY7C1382F A3 Burst continued with new base address Deselect cycle t CHZ Q( Q(A2) Q( Burst wraps around to its initial state is HIGH LOW HIGH ...
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... Data In (D) D(A1) High-Z t OEHZ ata Out (Q) BURST READ Single WRITE Note: 27. Full width write can be initiated by either GW LOW HIGH, BWE LOW and BW Document #: 38-05543 Rev. *E CY7C1380D, CY7C1380F CY7C1382D, CY7C1382F ADSC extends burst t WES t WEH ADV suspends burst D(A2 BURST WRITE DON’ ...
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... High-Z t OEHZ t CLZ Data Out (Q) Q(A1) Q(A2) High-Z Back-to-Back READs Notes: 28. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 29 HIGH. Document #: 38-05543 Rev. *E CY7C1380D, CY7C1380F CY7C1382D, CY7C1382F WES t WEH OELZ D(A3) Q(A4) Q(A4+1) Single WRITE BURST READ DON’ ...
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... DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05543 Rev ZZI I DDZZ High-Z DON’T CARE [ Truth Table on page 9 for all possible signal conditions to deselect the device. CY7C1380D, CY7C1380F CY7C1382D, CY7C1382F t ZZREC t RZZI DESELECT or READ Only Page [+] Feedback ...
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... Ball Grid Array ( 2.4 mm) Pb-Free CY7C1382F-200BGXI CY7C1380D-200BZI 51-85180 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) CY7C1382D-200BZI CY7C1380D-200BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) Pb-Free CY7C1382D-200BZXI Document #: 38-05543 Rev. *E CY7C1380D, CY7C1380F CY7C1382D, CY7C1382F Part and Package Type Operating Range Commercial Industrial Commercial Industrial ...
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... CY7C1382F-250BGI CY7C1380F-250BGXI 51-85115 119-ball Ball Grid Array ( 2.4 mm) Pb-Free CY7C1382F-250BGXI CY7C1380D-250BZI 51-85180 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) CY7C1382D-250BZI CY7C1380D-250BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) Pb-Free CY7C1382D-250BZXI Document #: 38-05543 Rev. *E CY7C1380D, CY7C1380F CY7C1382D, CY7C1382F Commercial Industrial ...
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... BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS A CY7C1380D, CY7C1380F CY7C1382D, CY7C1382F 1.40±0.05 12°±1° A SEE DETAIL (8X) 0 ...
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... Package Diagrams (continued) Figure 2. 119-ball BGA ( 2.4 mm) (51-85115) Document #: 38-05543 Rev. *E CY7C1380D, CY7C1380F CY7C1382D, CY7C1382F 51-85115-*B Page [+] Feedback ...
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... PACKAGE WEIGHT : 0.475g SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE WEIGHT : 0.475g PACKAGE CODE : BB0AC JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE CODE : BB0AC CY7C1380D, CY7C1380F CY7C1382D, CY7C1382F BOTTOM VIEW PIN 1 CORNER BOTTOM VIEW PIN 1 CORNER Ø0. Ø0. Ø ...
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... Document History Page Document Title: CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F, 18-Mbit (512K x 36/1M x 18) Pipelined SRAM Document Number: 38-05543 Orig. of REV. ECN NO. Issue Date Change ** 254515 See ECN RKF *A 288531 See ECN SYT *B 326078 See ECN PCI *C 416321 See ECN NXR *D 475009 See ECN VKN *E 776456 ...