cy7c1380d-250bzxi Cypress Semiconductor Corporation., cy7c1380d-250bzxi Datasheet - Page 15

• Manufacturer Part Number: cy7c1380d-250bzxi
• Description: 18-mbit 512k X 36/1m X 18 Pipelined Sram
• Manufacturer: Cypress Semiconductor Corporation.

Identification Register Definitions
Scan Register Sizes
Identification Codes
Note:
Document #: 38-05543 Rev. *E
13. Bit #24 is 1 in the register definitions for both 2.5v and 3.3v versions of this device.
Revision Number (31:29)
Device Depth (28:24)
Device Width (23:18) 119-BGA
Device Width (23:18) 165-FBGA
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
Instruction
Bypass
ID
Boundary Scan Order (119-ball BGA package)
Boundary Scan Order (165-ball FBGA package)
EXTEST
IDCODE
SAMPLE Z
RESERVED
SAMPLE/PRELOAD
RESERVED
RESERVED
BYPASS
Instruction
Instruction Field
Register Name
[13]
Code
001
010
000
011
100
101
110
111
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use. This instruction is reserved for future use.
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
Do Not Use. This instruction is reserved for future use.
Do Not Use. This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
CY7C1380D/CY7C1380F
00000110100
(512K x 36)
101000
000000
100101
01011
000
1
CY7C1382D/CY7C1382F
Bit Size (x36)
00000110100
(1 Mbit x 18)
32
85
89
3
1
010101
101000
000000
Description
01011
000
1
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Describes the version number.
Reserved for internal use.
Defines the memory type and
architecture.
Defines the memory type and
architecture.
Defines the width and density.
Allows unique identification of
SRAM vendor.
Indicates the presence of an ID
register.
Bit Size (x18)
Description
32
85
89
3
1
Page 15 of 30
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