ad73460 Analog Devices, Inc., ad73460 Datasheet - Page 24

• Manufacturer Part Number: ad73460
• Description: Six-input Channel Analog Front End
• Manufacturer: Analog Devices, Inc.

AD73460
When the IDLE (n) instruction is used, it effectively slows
down the processor’s internal clock and thus its response time to
incoming interrupts. The one-cycle response time of the stan-
dard idle state is increased by n, the clock divisor. When an
enabled interrupt is received, the AD73460 will remain in the
idle state for up to a maximum of n processor cycles (n = 16,
32, 64, or 128) before resuming normal operation.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
rate faster than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
SYSTEM INTERFACE
Figure 11 shows a typical basic system configuration with the
AD73460, two serial devices, a byte-wide EPROM, and
optional external program and data overlay memories (mode
selectable). Programmable wait state generation allows the pro-
cessor to easily connect to slow peripheral devices. The AD73460
also provides four external interrupts and two serial ports or six
external interrupts and one serial port. Host Memory Mode
allows access to the full external databus, but limits addressing
to a single address bit (A0). Additional system peripherals can
be added in this mode through the use of external hardware to
generate and latch address signals.
Clock Signals
The AD73460 can be clocked by either a crystal or a TTL
compatible clock signal.
The CLKIN input cannot be halted, changed during operation,
or operated below the specified frequency during normal operation.
The only exception is while the processor is in the power-down
state. For additional information, refer to Chapter 9, ADSP-
2100 Family User’s Manual, Third Edition, for detailed information
on this power-down feature.
If an external clock is used, it should be a TTL compatible
signal running at half the instruction rate. The signal is
connected to the processor’s CLKIN input. When an external
clock is used, the XTAL input must be left unconnected.
The AD73460 uses an input clock with a frequency equal to half
the instruction rate; a 26.00 MHz input clock yields a 19 ns
processor cycle (which is equivalent to 52 MHz). Normally,
instructions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.
Because the AD73460 includes an on-chip oscillator circuit, an
external crystal may be used. The crystal should be connected
across the CLKIN and XTAL pins, with two capacitors connected
as shown in Figure 12. Capacitor values are dependent on crystal
type and should be specified by the crystal manufacturer. A
parallel-resonant, fundamental frequency, microprocessor-grade
crystal should be used.
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled
by the CLK0DIS bit in the SPORT0 Autobuffer Control Register.
–24–
CONTROLLER
INTERFACE
SYSTEM
1/2x CLOCK
1/2x CLOCK
SECTION
SECTION
CRYSTAL
SECTION
SECTION
OR
CRYSTAL
DEVICE
DEVICE
SERIAL
SERIAL
DEVICE
DEVICE
SERIAL
SERIAL
AFE*
AFE*
AFE*
AFE*
OR
OR
OR
OR
OR
OR
Figure 12. External Crystal Connections
Figure 11. Basic System Configuration
16
FULL MEMORY MODE
CLKIN
MODE C/PF2
MODE B/PF1
MODE A/PF0
CLKIN
MODE C/PF2
MODE B/PF1
MODE A/PF0
HOST MEMORY MODE
IAD15–0
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SCLK0
RFS0
TFS0
DT0
DR0
FL0–2
PF3
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
XTAL
FL0–2
PF3
XTAL
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SCLK0
RFS0
TFS0
DT0
DR0
IRD/D6
IWR/D7
IS/D4
IAL/D5
IACK/D3
IDMA PORT
SPORT0
SPORT1
SPORT0
SPORT1
AD73460
AD73460
CLKIN
ADDR13–0
DATA23–8
DATA23–0
PWDACK
PWDACK
IOMS
IOMS
PWD
PWD
XTAL
BMS
DMS
CMS
BGH
BMS
DMS
CMS
BGH
PMS
PMS
WR
WR
RD
BR
BG
BR
BG
RD
A0
14
1
24
16
*AFE SECTION CAN BE
CONNECTED TO EITHER
SPORT0 OR SPORT1
CLKOUT
D
A
A
D
D
23–16
D
A
13–0
13–0
15–8
23–8
23–0
10–0
A0-A21
DATA
ADDR
DATA
DATA
CS
CS
ADDR
(PERIPHERALS)
PM SEGMENTS
DM SEGMENTS
LOCATIONS
I/O SPACE
MEMORY
OVERLAY
MEMORY
TWO 8K
TWO 8K
BYTE
2048
REV. A