ad73460 Analog Devices, Inc., ad73460 Datasheet - Page 30

• Manufacturer Part Number: ad73460
• Description: Six-input Channel Analog Front End
• Manufacturer: Analog Devices, Inc.

AD73460
The EZ-ICE uses the EE (emulator enable) signal to take
control of the AD73460 in the target system. This causes the
processor to use its ERESET, EBR, and EBG pins instead of
the RESET, BR, and BG pins. The BG output is three-stated.
These signals do not need to be jumper-isolated in your system.
The EZ-ICE connects to your target system via a ribbon cable
and a 14-pin female plug. The ribbon cable is 10 inches in length
with one end fixed to the EZ-ICE. The female plug is plugged
onto the 14-pin connector (a pin strip header) on the target board.
Target Board Connector for EZ-ICE Probe
The EZ-ICE connector (a standard pin strip header) is shown
in Figure 19. This connector must be added to the target
board design in order to use the EZ-ICE. Be sure to allow
enough room in the system to fit the EZ-ICE probe onto the
14-pin connector.
The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-
tion—Pin 7 must be removed from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spac-
ing should be 0.1 × 0.1 inches. The pin strip header must have
at least 0.15-inch clearance on all sides to accept the EZ-ICE
probe plug.
Pin strip headers are available from vendors such as 3M,
McKenzie, and Samtec.
Target Memory Interface
For the target system to be compatible with the EZ-ICE emu-
lator, it must comply with the memory interface guidelines
listed below.
PM, DM, BM, IOM, and CM
Design Program Memory (PM), Data Memory (DM), Byte
Memory (BM), I/O Memory (IOM), and Composite Memory
(CM) external interfaces to comply with worst-case
device timing requirements and switching characteristics as
specified in the DSP’s data sheet. The performance of the
EZ-ICE may approach published worst-case specification for
some memory access timing requirements and switching
characteristics.
Note: If the target does not meet the worst-case chip specifica-
tion for memory access parameters, user may not be able to
Figure 19. Target Board Connector for EZ-ICE
KEY (NO PIN)
ELOUT
RESET
GND
EBG
EBR
EE
11
13
1
3
5
7
9
TOP VIEW
12
14
10
2
4
6
8
BG
BR
EINT
ELIN
ECLK
EMS
ERESET
–30–
emulate the circuitry at the desired CLKIN frequency.
Depending on the severity of the specification violation, it may
create a problem manufacturing the system as DSP components
statistically vary in switching characteristic and timing require-
ments within published limits.
Restriction: All memory strobe signals on the AD73460 (RD,
WR, PMS, DMS, BMS, CMS, and IOMS) used in the target
system must have 10 kΩ pull-up resistors connected when the
EZ-ICE is being used. The pull-up resistors are necessary
because there are no internal pull-ups to guarantee their state
during prolonged three-state conditions resulting from typical
EZ-ICE debugging sessions. These resistors may be removed at
the user’s option when the EZ-ICE is not being used.
Target System Interface Signals
When the EZ-ICE board is installed, the performance on some
system signals changes. Design the system to be compatible with
the following system interface signal changes introduced by the
EZ-ICE board:
• EZ-ICE emulation introduces an 8 ns propagation delay
• EZ-ICE emulation introduces an 8 ns propagation delay
• EZ-ICE emulation ignores RESET and BR when single-
• EZ-ICE emulation ignores RESET and BR when in Emulator
• EZ-ICE emulation ignores the state of target BR in certain
ANALOG FRONT END (AFE) INTERFACING
The AFE section of the AD73460 features six input channels,
each with 16-bit linear resolution. Connectivity to the AFE
section from the DSP is uncommitted, thus allowing the user
the flexibility of connecting in the mode or configuration of their
choice. This section will detail several configurations—with no
extra AFE channels configured and with an extra AFE section
configured (using an external AD73360 AFE).
DSP SPORT TO AFE INTERFACING
The SCLK, SDO, SDOFS, SDI, and SDIFS must be connected
to the SCLK, DR, RFS, DT, and TFS pins of the DSP respec-
tively. The SE pin may be controlled from a parallel output pin
or flag pin such as FL0–2 or, where SPORT power-down is not
required, it can be permanently strapped high using a suitable
pull-up resistor. For consistent performance, the SE pin should
be synchronized to the rising edge of the AMCLK using a cir-
cuit similar to that of Figure 23. The ARESET pin may be
connected to the system hardware reset structure or it may also
be controlled using a dedicated control line. In the event of
tying it to the global system reset, it is necessary to operate the
device in mixed mode, which allows a software reset. Otherwise
there is no convenient way of resetting the device.
between the target circuitry and the DSP on the RESET
signal.
between the target circuitry and the DSP on the BR signal.
stepping.
Space (DSP halted).
modes. As a result, the target system may take control of the
DSP’s external memory bus only if bus grant (BG) is asserted
by the EZ-ICE board’s DSP.
REV. A