ad73460 Analog Devices, Inc., ad73460 Datasheet - Page 25

• Manufacturer Part Number: ad73460
• Description: Six-input Channel Analog Front End
• Manufacturer: Analog Devices, Inc.

RESET
The RESET signal initiates a master reset of the AD73460. The
RESET signal must be asserted during the power-up sequence
to assure proper initialization. RESET during initial power-up
must be held long enough to allow the internal clock to stabi-
lize. If RESET is activated any time after power-up, the clock
continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V
to the processor, and for the internal phase-locked loop (PLL)
to lock onto the specific crystal frequency. A minimum of 2000
CLKIN cycles ensures that the PLL has locked, but does not
include the crystal oscillator start-up time. During this power-up
sequence, the RESET signal should be held low. On any
subsequent resets, the RESET signal must meet the mini-
mum pulsewidth specification, t
The RESET input contains some hysteresis; however, if an RC
circuit is used to generate the RESET signal, an external Schmitt
trigger is recommended.
The master reset sets all internal stack pointers to the empty stack
condition, masks all interrupts, and clears the MSTAT register.
When RESET is released, if there is no pending bus request
and the chip is configured for booting, the boot-loading sequence
is performed. The first instruction is fetched from on-chip
program memory location 0x0000 once boot loading completes.
MODES OF OPERATION
Table XVIII summarizes the AD73460 memory modes.
Setting Memory Mode
Memory Mode selection for the AD73460 is made during chip
reset through the use of the Mode C pin. This pin is multi-
plexed with the DSP’s PF2 pin, so care must be taken in how
the mode selection is made. The two methods for selecting the
value of Mode C are active and passive.
REV. A
MODE C
0
0
1
1
NOTES
1
2
3
4
5
All mode pins are recognized while RESET is active (low).
When Mode C = 0, Full Memory enabled. When Mode C = 1, Host Memory Mode enabled.
When Mode B = 0, Auto Booting enabled. When Mode B = 1, no Auto Booting.
When Mode A = 0, BDMA enabled. When Mode A = 1, IDMA enabled.
Considered as standard operating settings. Using these configurations allows for easier design and better memory management.
2
MODE B
0
1
0
0
3
MODE A
0
0
0
1
RSP
.
4
memory space. Program execution is held off until all 32 words have been loaded.
Chip is configured in Full Memory Mode.
location 0. Chip is configured in Full Memory Mode. BDMA can still be used, but
the processor does not automatically use or wait for these operations.
memory space. Program execution is held off until all 32 words have been loaded.
Chip is configured in Host Mode. (REQUIRES ADDITIONAL HARDWARE.)
held off until internal program memory location 0 is written to. Chip is configured in
Host Mode.
Booting Method
BDMA feature is used to load the first 32 program memory words from the byte
No automatic boot operations occur. Program execution starts at external memory
BDMA feature is used to load the first 32 program memory words from the byte
IDMA feature is used to load any internal memory as desired. Program execution is
Table XVIII. Modes of Operation
DD
is applied
5
–25–
Passive Configuration involves the use of a pull-up or pull-down
resistor connected to the Mode C pin. To minimize power
consumption, or if the PF2 pin is to be used as an output in the
DSP application, a weak pull-up or pull-down, on the order of
100 kΩ, can be used. This value should be sufficient to pull the
pin to the desired level and still allow the pin to operate as a
programmable flag output without undue strain on the processor’s
output driver. For minimum power consumption during power-
down, reconfigure PF2 to be an input, as the pull-up or pull-down
will hold the pin in a known state, and will not switch.
Active Configuration involves the use of a three-statable
external driver connected to the Mode C pin. A driver’s output
enable should be connected to the DSP’s RESET signal such
that it only drives the PF2 pin when RESET is active (low).
When RESET is deasserted, the driver should three-state, thus
allowing full use of the PF2 pin as either an input or output. To
minimize power consumption during power-down, configure the
programmable flag as an output when connected to a three-stated
buffer. This ensures that the pin will be held at a constant level and
not oscillate should the three-state driver’s level hover around
the logic switching point.
MEMORY ARCHITECTURE
The AD73460 provides a variety of memory and peripheral
interface options. The key functional groups are Program Memory,
Data Memory, Byte Memory, and I/O. Refer to the following
figures and tables for PM and DM memory allocations in the
AD73460.
PROGRAM MEMORY
Program Memory (Full Memory Mode) is a 24-bit-wide
space for storing both instruction opcodes and data. The
AD73460-80 has 16K words of Program Memory RAM on-chip
(the AD73460-40 has 8K words of Program Memory RAM
on-chip), and the capability of accessing up to two 8K external
memory overlay spaces using the external databus.
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AD73460