mt48h8m16lf Micron Semiconductor Products, mt48h8m16lf Datasheet - Page 36

• Manufacturer Part Number: mt48h8m16lf
• Description: 128mb 8 Meg X 16, 4 Meg X 32 Mobile Sdram
• Manufacturer: Micron Semiconductor Products

Burst Type
Table 19:
CAS Latency (CL)
PDF: 09005aef832ff1ea / Source: 09005aef832ff1ac
sdr_mobile_sdram_cmd_op_timing_dia_fr5.08__4.fm - Rev. B 6/08 EN
Burst Length
Continuous
2
4
8
Burst Definition Table
n = A0–An/9/8 (location 0–y)
Starting Column Address
A2
0
0
0
0
1
1
1
1
A[8:1] when BL = 2, A[8:2] when BL = 4, and A[8:3] when BL = 8. The remaining (least
significant) address bit(s) is (are) used to select the starting location within the block.
Continuous page burst wraps within the page if the boundary is reached.
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the BL, the burst type, and the
starting column address, as shown in Table 19.
The CL is the delay, in clock cycles, between the registration of a READ command and
the availability of the first piece of output data. The latency can be set to two or three
clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available by clock edge n + m. The DQs start driving as a result of the clock edge
one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data
is valid by clock edge n + m. For example, assuming that the clock cycle time is such that
all relevant access times are met, if a READ command is registered at T0 and the latency
is programmed to two clocks, the DQs start driving after T1 and the data is valid by T2, as
shown in Figure 14.
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
A1
A1
0
0
1
1
0
0
1
1
0
0
1
1
A0
A0
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
Type = Sequential
36
Cn + 3...Cn - 1, Cn...
Cn, Cn + 1, Cn + 2,
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1
1-0
Order of Accesses Within a Burst
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Type = Interleaved
©2008 Micron Technology, Inc. All rights reserved.
Register Definition
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not supported
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0
Preliminary