mt47h256m8thn-3 Micron Semiconductor Products, mt47h256m8thn-3 Datasheet - Page 10

• Manufacturer Part Number: mt47h256m8thn-3
• Description: 2gb X4, X8 Twindie Ddr2 Sdram Functionality
• Manufacturer: Micron Semiconductor Products

Table 7:
PDF: 09005aef8266acfe/Source: 09005aef8266ac6e
MT47H512M4_32M_16M_twindie.fm - Rev. B 1/08 EN
Parameter/Condition
Operating burst read current: All banks open;
Continuous burst reads; I
CL = CL (I
t
HIGH, CS# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs
are switching (inactive die is in I
but with inputs switching)
Burst refresh current:
command at every
CS# is HIGH between valid commands; Other
control and address bus inputs are switching; Data
bus inputs are switching (inactive die is in I
condition, but with inputs switching)
Self refresh current: CK and CK# at 0V;
CKE ≤ 0.2V; Other control and address bus inputs
are floating; Data bus inputs are floating
Operating bank interleave read current: All
banks interleaving reads; I
CL = CL (I
t
t
between valid commands; Address bus inputs are
stable during deselects; Data bus inputs are
switching (inactive die is in I
with inputs switching)
RAS =
CK =
RCD =
t
CK (I
t
t
RAS MAX (I
RCD (I
DD
DD
DD
), AL = 0;
), AL =
DDR2 I
Notes: 1–7 apply to the entire document; notes appear on page 10
),
DD
t
RC =
); CKE is HIGH, CS# is HIGH
t
Notes:
t
DD
RCD (I
RFC (I
t
t
),
CK =
CDD
RC (I
t
RP =
t
OUT
CK =
DD
DD
OUT
DD
Specifications and Conditions (continued)
t
) interval; CKE is HIGH,
CK (I
1. I
2. I
3. Data bus consists of DQ, DM, DQS, DQS#, RDQS, and RDQS#.
4. I
5. Definitions for I
6. I
7. I
DD
) - 1 ×
= 0mA; BL = 4,
),
t
RP (I
5b. HIGH: V
5d. Floating: Inputs at V
5a. LOW: V
5e. Switching: Inputs changing between HIGH and LOW every other clock cycle (once per
t
= 0mA; BL = 4,
5c. Stable: Inputs stable at a HIGH or LOW level
2P condition, but
5f. Switching: Inputs changing between HIGH and LOW every other data transfer (once per
t
CK (I
V
ual die values.
RRD =
CDD
CDD
CDD
DD
CDD
DD
DD
DD
1, I
DD
2P condition,
two clocks) for address and control signals
clock) for DQ signals, not including masks or strobes
),
t
/I
/I
/I
/I
CK (I
DD
= V
DD
DD
DD
DD
); CKE is
DD
); REFRESH
t
RRD (I
DD
specifications are tested after the device is properly initialized. 0°C ≤ T
parameters are specified with ODT disabled.
values must be met with all combinations of EMR bits 10 and 11.
values reflect the combined current of both individual die. I
4R, and I
DD
Q = +1.8V ±0.1V; V
IN
IN
);
DD
≤ V
≥ V
DD
2P
CDD
IL
),
IH
DD
(
AC
(
/I
AC
7 require EMR1, A12 to be enabled during testing.
DD
) MAX
Combined
) MIN
Symbol
I
conditions:
CDD
I
I
I
REF
CDD
CDD
CDD
4R
= V
5
6
7
10
DD
DD
L = +1.8V ±0.1V; V
Q/2
I
DD
I
I
DD
DD
Die Status
Individual
4R + I
I
5 + I
DD
7 + I
I
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CDD
I
I
I
CDD
CDD
CDD
6 + I
DD
DD
4R =
DD
5 =
6 =
7 =
2Gb: x4, x8 TwinDie DDR2 SDRAM
DD
2P + 5
2P + 5
2P + 5
6
REF
= V
Width
x4, x8
x4, x8
x4, x8
Bus
DD
x4
x8
Electrical Specifications
Q/2.
©2006 Micron Technology, Inc. All rights reserved
-25E
-25/
157
172
247
347
14
DDX
132
147
227
292
represents individ-
14
-3
-37E Units
C
122
137
222
282
14
≤ +85°C.
mA
mA
mA
mA