mt47h256m8thn-3 Micron Semiconductor Products, mt47h256m8thn-3 Datasheet - Page 5

• Manufacturer Part Number: mt47h256m8thn-3
• Description: 2gb X4, X8 Twindie Ddr2 Sdram Functionality
• Manufacturer: Micron Semiconductor Products

Table 3:
Functional Description
PDF: 09005aef8266acfe/Source: 09005aef8266ac6e
MT47H512M4_32M_16M_twindie.fm - Rev. B 1/08 EN
A9, C1, C3, C7,
A7, B2, B8, D2,
A2, B1, B9, D1,
Ball Numbers
A3, E3, J1, K9
A2, A8
L3, L7
C9
D8
D9
E1
E2
E7
63-Ball FBGA Ball Descriptions – x4, x8 (continued)
Symbol
V
V
V
V
V
RFU
V
NU
SS
DD
NF
DD
SS
REF
SS
DL
Q
Q
L
The 2Gb (TwinDie) DDR2 SDRAM is a high-speed, CMOS dynamic random access
memory device containing 2,147,483,648 bits and is internally configured as two 8-bank
1Gb DDR2 SDRAM devices.
Although each die is tested individually within the dual-die package, some TwinDie test
results may vary from a like-die tested within a monolithic die package.
Each DDR2 SDRAM die uses a double data rate architecture to achieve high-speed oper-
ation. The DDR2 architecture is essentially a 4n-prefetch architecture, with an interface
designed to transfer two data words per clock cycle at the I/O balls. A single read or write
access consists of a single 4n-bit-wide, one-clock-cycle data transfer at the internal
DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at
the I/O balls.
Addressing of the TwinDie is identical to the monolithic device. Additionally, multiple
chip selects select the desired rank.
This TwinDie data sheet is intended to provide a general description, package dimen-
sions, and the ballout only. Refer to the Micron 1Gb DDR2 data sheet for complete infor-
mation regarding individual die initialization, register definition, command
descriptions, and die operation.
Supply
Supply
Supply
Supply
Supply
Supply
Type
–
–
–
Description
DLL power supply: 1.8V ±0.1V.
DQ power supply: 1.8V ±0.1V. Isolated on the device for improved noise
immunity.
SSTL_18 reference voltage (V
Ground.
DLL ground: Isolated on the device from V
DQ ground: Isolated on the device for improved noise immunity.
No function: These balls provide no function on the x4 configuration only.
Not used: For the x8 configuration only. If EMR(E10) = 0, A2 is RDQS# and A8
is DQS#. If EMR(E10) = 1, then A2 and A8 are not used.
Reserved for future use: Row address bits A14 and A15.
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
Q/2).
2Gb: x4, x8 TwinDie DDR2 SDRAM
SS
and V
Functional Description
SS
©2006 Micron Technology, Inc. All rights reserved
Q.