mt45w4mw16bcgb Micron Semiconductor Products, mt45w4mw16bcgb Datasheet - Page 28

• Manufacturer Part Number: mt45w4mw16bcgb
• Description: 64mb 4 Meg X 16 Async/page/burst Cellularram 1.5 Memory
• Manufacturer: Micron Semiconductor Products

Figure 20:
Figure 21:
Latency Counter (BCR[13:11]) Default = Three Clock Latency
Initial Access Latency (BCR[14]) Default = Variable
Operating Mode (BCR[15]) Default = Asynchronous Operation
PDF: 09005aef8247bd51/Source: 09005aef8247bd83
64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN
DQ[15:0]
WAIT
WAIT
CLK
WAIT Configuration (BCR[8] = 1)
WAIT Configuration During Burst Operation
Note:
Note:
DQ[15:0]
The latency counter bits determine how many clocks occur between the beginning of a
READ or WRITE operation and the first data value transferred. For allowable latency
codes, see Tables 6 and 7 on pages 29 and 30, respectively, and Figures 22 and 23 on
pages 29 and 30, respectively.
Variable initial access latency outputs data after the number of clocks set by the latency
counter. However, WAIT must be monitored to detect delays caused by collisions with
refresh operations.
Fixed initial access latency outputs the first data at a consistent time that allows for
worst-case refresh collisions. The latency counter must be configured to match the
initial latency and the clock frequency. It is not necessary to monitor WAIT with fixed
initial latency. The burst begins after the number of clock cycles configured by the
latency counter (see Table 7 on page 30 and Figure 23 on page 30).
The operating mode bit either selects synchronous burst operation or the default asyn-
chronous mode of operation.
WAIT
Valid/invalid data delayed for one clock after WAIT transitions (BCR[8] = 1). See Figure 21
on page 28).
Nondefault BCR setting: WAIT active LOW.
CLK
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory
D[0]
High-Z
D[1]
Data 0
28
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D[2]
Don’t Care
D[3]
©2005 Micron Technology, Inc. All rights reserved.
BCR[8] = 0
Data valid in current cycle
BCR[8] = 1
Data valid in next cycle
Registers