mt45w4mw16bcgb Micron Semiconductor Products, mt45w4mw16bcgb Datasheet - Page 41

• Manufacturer Part Number: mt45w4mw16bcgb
• Description: 64mb 4 Meg X 16 Async/page/burst Cellularram 1.5 Memory
• Manufacturer: Micron Semiconductor Products

Table 19:
PDF: 09005aef8247bd51/Source: 09005aef8247bd83
64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN
Parameter
Address and ADV# LOW setup time
Address hold from ADV# HIGH (fixed latency)
CE# HIGH between subsequent burst or mixed-
mode operations
Maximum CE# pulse width
CE# LOW to WAIT valid
Clock period
CE# setup to CLK active edge
Hold time from active CLK edge
Chip disable to WAIT High-Z output
CLK rise or fall time
CLK to WAIT valid Variable LC = 4
CLK HIGH or LOW time
Setup time to active CLK edge
Burst WRITE Cycle Timing Requirements
Notes:
Fixed LC = 8
All other LCs
1.
2. A refresh opportunity must be provided every
3. Low-Z to High-Z timings are tested with the circuit shown in Figure 27 on page 37. The
t
either of the following two conditions: a) clocked CE# HIGH or b) CE# HIGH for longer than
15ns.
High-Z timings measure a 100mV transition either from V
AS is required if
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory
t
CSP > 20ns.
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
AS
AVH
CBPH
CEM
CEW
CLK
CSP
HD
HZ
KHKL
KHTL
KP
SP
41
Min
(133 Mhz)
7.5
2.5
1.5
0
2
5
1
3
2
–
–
–
–
–
-7013
Max
Micron Technology, Inc., reserves the right to change products or specifications without notice.
7.5
1.2
5.5
–
–
–
4
–
–
–
7
7
–
–
t
Min
9.62
(104 MHz)
CEM. A refresh opportunity is satisfied by
0
2
5
1
3
2
3
3
–
–
–
–
–
-701
Max
7.5
1.6
–
–
–
4
–
–
–
8
7
7
–
–
OH
or V
Timing Requirements
Min
12.5
(80 MHz)
0
2
6
–
1
4
2
–
–
–
–
4
3
©2005 Micron Technology, Inc. All rights reserved.
OL
-708
toward V
Max
7.5
1.8
–
–
–
4
–
–
–
8
9
9
–
–
Unit
CC
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Q/2.
Notes
1
2
2
3