mt45w8mw16bgx Micron Semiconductor Products, mt45w8mw16bgx Datasheet - Page 5

• Manufacturer Part Number: mt45w8mw16bgx
• Description: 128mb 8 Meg X 16 Async/page/burst Cellularram 1.5 Async/ Page/burst Cellularram 1.5 Memory
• Manufacturer: Micron Semiconductor Products

General Description
PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65
128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN
Micron
developed for low-power, portable applications. The MT45W8MW16BGX device has a
128Mb DRAM core, organized as 8 Meg x 16 bits. These devices include an industry-
standard burst mode Flash interface that dramatically increases read/write bandwidth
compared with other low-power SRAM or pseudo-SRAM offerings.
To operate seamlessly on a burst Flash bus, CellularRAM products incorporate a trans-
parent self refresh mechanism. The hidden refresh requires no additional support from
the system memory controller and has no significant impact on device read/write
performance.
Two user-accessible control registers define device operation. The bus configuration
register (BCR) defines how the CellularRAM device interacts with the system memory
bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh
configuration register (RCR) is used to control how refresh is performed on the DRAM
array. These registers are automatically loaded with default settings during power-up
and can be updated anytime during normal operation.
Special attention has been focused on standby current consumption during self refresh.
CellularRAM products include three mechanisms to minimize standby current. Partial-
array refresh (PAR) enables the system to limit refresh to only that part of the DRAM
array that contains essential data. Temperature-compensated refresh (TCR) uses an on-
chip sensor to adjust the refresh rate to match the device temperature—the refresh rate
decreases at lower temperatures to minimize current consumption during standby.
Deep power-down (DPD) enables the system to halt the refresh operation altogether
when no vital information is stored in the device. The system-configurable refresh
mechanisms are accessed through the RCR.
This CellularRAM device is compliant with the industry-standard CellularRAM 1.5
feature set established by the CellularRAM Workgroup. It includes support for both vari-
able and fixed latency, with three output-device drive-strength settings, additional wrap
options, and a device ID register (DIDR).
®
128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/
CellularRAM™ is a high-speed, CMOS pseudo-static random access memory
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
Page/Burst CellularRAM 1.5 Memory
©2004 Micron Technology, Inc. All rights reserved.