ics8430ay62l Integrated Device Technology, ics8430ay62l Datasheet - Page 2

• Manufacturer Part Number: ics8430ay62l
• Description: Ics8430-62 500mhz, Crystal-to-3.3v, 2.5v Differential Lvpecl Frequency Synthesizer
• Manufacturer: Integrated Device Technology

ICS8430-62 Datasheet
Functional Description
NOTE: The functional description that follows describes operation
using a 16MHz crystal. Valid PLL loop divider values for different
crystal or input frequencies are defined in the Input Frequency
Characteristics, Table 5, NOTE 1.
The ICS8430-62 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth. A
parallel-resonant, fundamental crystal is used as the input to the
on-chip oscillator. The output of the oscillator is divided by 16 prior to
the phase detector. With a 16MHz crystal, this provides a 1MHz
reference frequency. The VCO of the PLL operates over a range of
250MHz to 500MHz. The output of the M divider is also applied to the
phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high
or too low), the PLL will not achieve lock. The output of the VCO is
scaled by a divider prior to being sent to each of the LVPECL output
buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS8430-62 support two input
modes to program the M divider and N output divider. The two input
operational modes are parallel and serial. Figure 1 shows the timing
diagram for each mode. In parallel mode, the nP_LOAD input is
initially LOW. The data on inputs M0 through M8 and N0 through N2
is passed directly to the M divider and N output divider. On the
LOW-to-HIGH transition of the nP_LOAD input, the data is latched
and the M divider remains loaded until the next LOW transition on
nP_LOAD or until a serial event occurs. As a result, the M and N bits
can be hard-wired to set the M divider and N output divider to a
specific default state that will automatically occur during power-up.
ICS8430AY-62 REVISION A JULY 2, 2009
M0:M8, N0:N2
Figure 1. Parallel & Serial Load Operations
S_CLOCK
nP_LOAD
nP_LOAD
S_LOAD
S_LOAD
S_DATA
t
S
T1
t
H
T0
N2
t
M, N
S
N1
t
H
Time
N0
P
S
ARALLEL
ERIAL
2
M8
The TEST output is LOW when operating in the parallel input mode.
The relationship between the VCO frequency, the crystal frequency
and the M divider is defined as follows:
fVCO = fXTAL x M
The M value and the required values of M0 through M8 are shown in
Table 3B, Programmable VCO Frequency Function Table. Valid M
values for which the PLL will achieve lock for a 16MHz reference are
defined as 250 ≤ M ≤ 500. The frequency out is defined as follows:
fout = fVCO = fXTAL x M
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits with
the rising edge of S_CLOCK. The contents of the shift register are
loaded into the M divider and N output divider when S_LOAD
transitions from LOW-to-HIGH. The M divide and N output divide
values are latched on the HIGH-to-LOW transition of S_LOAD. If
S_LOAD is held HIGH, data at the S_DATA input is passed directly to
the M divider and N output divider on each rising edge of S_CLOCK.
The serial mode can be used to program the M and N bits and test
bits T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
L
T1
0
0
1
1
OADING
M7
L
OADING
N
M6
T0
0
1
0
1
16
M5
16
TEST Output
LOW
S_DATA, Shift Register Input
Output of M Divider
Do Not Use
M4
N
M3
M2
©2009 Integrated Device Technology, Inc.
M1
M0
t
S