ics8430-111 Integrated Device Technology, ics8430-111 Datasheet
ics8430-111
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ics8430-111 Summary of contents
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... Output frequencies up to 700MHz can be programmed using the serial or parallel inter- faces to the configuration logic. The low jitter and frequency range of the ICS8430-111 makes it an ideal clock generator for most clock tree applications ...
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... F D UNCTIONAL ESCRIPTION The ICS8430-111 features a fully integrated PLL and there- fore requires no external components for setting the loop bandwidth. A differential clock input is used as the input to the on-chip oscillator. The output of the oscillator is divided by 16 prior to the phase detector. A16MHz clock input provides a 1MHz reference frequency ...
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... ICS8430-111 700MHZ, LOW JITTER, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER ABLE IN ESCRIPTIONS ...
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... ICS8430-111 700MHZ, LOW JITTER, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER T 3A ABLE ARALLEL AND ERIAL ODE ↑ ↑ ...
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... ICS8430-111 700MHZ, LOW JITTER, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER BSOLUTE AXIMUM ATINGS Supply Voltage Inputs, V -0. Outputs Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θ 47.9°C/W (0 lfpm) JA Storage Temperature, T -65°C to 150°C STG T 4A ...
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... ICS8430-111 700MHZ, LOW JITTER, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER T 4C ABLE IFFERENTIAL HARACTERISTICS ...
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... ICS8430-111 700MHZ, LOW JITTER, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER ABLE HARACTERISTICS ...
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... ICS8430-111 700MHZ, LOW JITTER, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER P ARAMETER CCA V CCO LVPECL V EE -1.3V ± 0.165V 3. UTPUT OAD EST IRCUIT nFOUTx FOUTx nFOUTy FOUTy tsk( UTPUT KEW nFOUTx FOUTx tcycle n tjit(cc) = tcycle n – tcycle n+1 1000 Cycles ...
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... UPPLY ILTERING ECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8430-111 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10Ω ...
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... ICS8430-111 700MHZ, LOW JITTER, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER IRING THE IFFERENTIAL NPUT TO Figure 3 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio ...
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... ICS8430-111 700MHZ, LOW JITTER, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER IFFERENTIAL LOCK NPUT NTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V SWING V and V input requirements. Figures show interface PP CMR examples for the HiPerClockS CLK/nCLK input driven by the most common driver types ...
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... ICS8430-111 700MHZ, LOW JITTER, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER T 3.3V LVPECL O ERMINATION FOR The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs ...
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... Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8430-111 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for V NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. ...
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... ICS8430-111 700MHZ, LOW JITTER, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage ...
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... Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs RANSISTOR OUNT The transistor count for ICS8430-111 is: 3960 IDT ™ / ICS ™ 3.3V LVPECL FREQUENCY SYNTHESIZER R ...
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... ICS8430-111 700MHZ, LOW JITTER, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER ACKAGE UTLINE UFFIX FOR T Reference Document: JEDEC Publication 95, MS-026 IDT ™ / ICS ™ 3.3V LVPECL FREQUENCY SYNTHESIZER LQFP EAD Thermal Pad Down ABLE ACKAGE IMENSIONS ...
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... ICS8430-111 700MHZ, LOW JITTER, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER T 10 ABLE RDERING NFORMATION ...
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... ICS8430-111 700MHZ, LOW JITTER, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) © ...