ics87931i-147 Integrated Device Technology, ics87931i-147 Datasheet
ics87931i-147
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ics87931i-147 Summary of contents
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... PLL to be bypassed. When LOW, the nMR input re- sets the internal dividers and forces the outputs to the high impedance state. The effective fanout of the ICS87931I-147 can be increased utilizing the ability of each output to drive two series terminated transmission lines. ...
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... ICS87931I-147 LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER ABLE IN ESCRIPTIONS ...
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... ICS87931I-147 LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER T 3A ABLE ONTROL NPUT UNCTION ...
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... ICS87931I-147 LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER VCO VCO/2 POWER_DN QA(÷2) QB(÷4) QC(÷ CLK_EN0 CLK_EN1 QA(÷2) QB(÷4) QC(÷6) CLK_EN0 CLK_EN1 IDT ™ / ICS ™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER F 1A. POWER_DN T D IGURE IMING IAGRAM F 1B. CLK_EN T D IGURE ...
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... ICS87931I-147 LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER BSOLUTE AXIMUM ATINGS Supply Voltage Inputs, V -0. Outputs, V -0. Package Thermal Impedance, θ JA Storage Temperature, T -65°C to 150°C STG T 5A ABLE OWER UPPLY HARACTERISTICS ...
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... ICS87931I-147 LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER T 6. PLL ABLE NPUT EFERENCE HARACTERISTICS ...
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... ICS87931I-147 LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER P ARAMETER 1.65V±5% V DDA, V DDO LVCMOS GND GND = -1.165V±5% 3. UTPUT OAD EST IRCUIT V DDO DDO 2 Qy tsk( UTPUT KEW 2V 0.8V Clock t Outputs UTPUT ISE ALL IME V QAx, QBx, QCx ...
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... ICS87931I-147 LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER IRING THE IFFERENTIAL NPUT TO Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio ...
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... ICS87931I-147 LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER IFFERENTIAL LOCK NPUT NTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. The signals must meet the V V input requirements. Figures show interface examples CMR for the HiPerClockS CLK/nCLK input driven by the most common driver types ...
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... VDDA POWER_DN 3 POWER_DN 4 CLK1 5 nMR EXTFB_SEL 6 CLK0 CLK_SEL 7 nCLK0 PLL_SEL 8 GND R8 R9 ICS87931I ICS87931I-147 50 50 R10 50 (U1-13) VDD=3. Space (i.e. not intstalled) F 4A. ICS87931I-147 S IGURE CHEMATIC 10 pin as possible. DDA VDD VDD 24 GND QB0 QB1 21 VDDO ...
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... Make sure no other signal traces are routed between the clock trace pair. • The series termination resistors should be located as close to the driver pins as possible. 50 Ohm Trace Pin Ohm Trace F 4B. PCB IGURE OARD AYOUT OR 11 GND VCC VIA Other signals C2 ICS87931I-147 ICS87931AYI-147 REV. A MARCH 29, 2007 ...
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... F T ABLE VS IR LOW ABLE FOR JA Multi-Layer PCB, JEDEC Standard Test Boards T C RANSISTOR OUNT The transistor count for ICS87931I-147 is: 2942 Pin compatible with MPC931, MPC9331 IDT ™ / ICS ™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER R I ELIABILITY NFORMATION 32 L LQFP EAD θ ...
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... ICS87931I-147 LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER ACKAGE UTLINE UFFIX FOR ABLE Reference Document: JEDEC Publication 95, MS-026 IDT ™ / ICS ™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER LQFP EAD D ACKAGE IMENSIONS ...
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... ICS87931I-147 LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER T 10 ABLE RDERING NFORMATION ...
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... ICS87931I-147 LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) © ...