ics87931i-147 Integrated Device Technology, ics87931i-147 Datasheet - Page 8

• Manufacturer Part Number: ics87931i-147
• Description: Low Skew, 1-to-6 Lvcmos/lvttl Clock Multiplier/zero Delay Buffer
• Manufacturer: Integrated Device Technology

W
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
R
I
CLK I
For applications not requiring the use of a clock input, it can be
left floating. Though not required, but for additional protection, a
1kΩ resistor can be tied from the CLK input to ground.
CLK/nCLK I
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required, but
for additional protection, a 1kΩ resistor can be tied from CLK to
ground.
LVCMOS C
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
IDT
NPUTS
ECOMMENDATIONS FOR
ICS87931I-147
LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
IRING THE
™
/ ICS
NPUT
:
™
:
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
ONTROL
NPUT
D
IFFERENTIAL
:
P
INS
:
U
NUSED
I
NPUT TO
F
IGURE
I
NPUT AND
Single Ended Clock Input
A
CCEPT
2. S
A
PPLICATION
INGLE
O
S
UTPUT
INGLE
E
C1
0.1u
NDED
V_REF
DD
/2 is
E
P
NDED
S
INS
IGNAL
8
I
L
NFORMATION
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
and R2/R1 = 0.609.
O
LVCMOS O
All unused LVCMOS output can be left floating. There should be
no trace attached.
D
EVELS
1K
R1
1K
R2
UTPUTS
RIVING
VDD
D
CLK
nCLK
:
IFFERENTIAL
UTPUTS
:
I
NPUT
ICS87931AYI-147 REV. A MARCH 29, 2007
DD
= 3.3V, V_REF should be 1.25V