ics8745b Integrated Device Technology, ics8745b Datasheet
ics8745b
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ics8745b Summary of contents
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... DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Description The ICS8745B is a highly versatile 1:5 LVDS Clock ICS Generator and a member of the HiPerClockS™ f family of High Performance Clock Solutions from HiPerClockS™ IDT. The ICS8745B has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 31 ...
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... Differential output pair. LVDS interface levels. Analog supply pin. PLL select. Selects between the PLL and reference clock as the input to the Pullup dividers. When LOW, selects reference clock. LVCMOS/LVTTL interface levels. Test Conditions 2 Minimum Typical Maximum ICS8745BYREV. C OCTOBER 27, 2008 Units pF k Ω k Ω ...
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... Outputs PLL_SEL = 1 PLL Enable Mode Q0:Q4/Q0:Q4 ÷1 ÷1 ÷1 ÷1 ÷2 ÷2 ÷2 ÷4 ÷4 ÷ ICS8745BYREV. C OCTOBER 27, 2008 ...
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... IDT™ / ICS™ LVDS ZERO DELAY CLOCK GENERATOR Outputs PLL_SEL = 0 PLL Bypass Mode SEL0 Q0:Q4/Q0:Q4 0 ÷4 1 ÷4 0 ÷4 1 ÷8 0 ÷8 1 ÷8 0 ÷16 1 ÷16 0 ÷32 1 ÷64 0 ÷2 1 ÷2 0 ÷4 1 ÷1 0 ÷2 1 ÷1 4 ICS8745BYREV. C OCTOBER 27, 2008 ...
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... 3.465V 0. 0°C to 70°C A Typical Maximum 3.3 3.465 3.3 3.465 3.3 3.465 125 0°C to 70°°C A Minimum Typical Maximum 0.3 DD -0.3 0.8 150 5 -5 -150 ICS8745BYREV. C OCTOBER 27, 2008 Units Units V V µA µA µA µA ...
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... Minimum Typical Maximum 150 -5 -150 0.15 1.3 GND + 0 0.3V 0°C to 70°C A Minimum Typical Maximum 320 440 550 0 50 1.05 1.2 1. 0°C to 70°C A Minimum Typical Maximum 31.25 700 700 ICS8745BYREV. C OCTOBER 27, 2008 Units µA 5 µA µA µA V – 0.85 V Units Units µA V ...
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... IDT™ / ICS™ LVDS ZERO DELAY CLOCK GENERATOR = 3.3V ± 5 0°C to 70°C DDA DDO A Test Conditions PLL_SEL = 0V, f ≤ 700MHz PLL_SEL = 3.3V 20% to 80% 7 Minimum Typical Maximum 700 3.1 3.4 4.0 -100 25 150 35 30 ±52 1 200 700 ICS8745BYREV. C OCTOBER 27, 2008 Units MHz ...
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... IDT™ / ICS™ LVDS ZERO DELAY CLOCK GENERATOR V DD SCOPE CLK[0:1] Qx CLK[0:1] nQx GND Differential Input Level the mean Output Skew Clock ➤ tcycle n+1 Outputs Output Rise/Fall Time 8 V Cross Points PP tsk(o) 80% 80% 20 ICS8745BYREV. C OCTOBER 27, 2008 V CMR V OD 20% ...
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... Offset Voltage Setup IDT™ / ICS™ LVDS ZERO DELAY CLOCK GENERATOR CLK[0:1] CLK[0:1] Q[0:4] Q[0:4] x 100% Propagation Delay out ➤ DC Input out V /∆ Differential Output Voltage Setup LVDS 100 ICS8745BYREV. C OCTOBER 27, 2008 out ➤ V /∆ ➤ out ...
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... DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8745B provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL ...
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... CLK nCLK HiPerClockS Input R2 84 Figure 3D. HiPerClockS CLK/CLK Input Driven 50Ω 50Ω LVPECL Driven by a 3.3V LVPECL Driver Zo = 50Ω R1 100 Zo = 50Ω LVDS a 3.3V LVDS Driver ICS8745BYREV. C OCTOBER 27, 2008 3.3V CLK nCLK HiPerClockS Input 3.3V CLK nCLK Receiver ...
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... All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, we recommend that there is no trace attached. For a multiple LVDS outputs buffer, if only partial outputs are used recommended to terminate the unused outputs. 50Ω 100Ω – 50Ω 12 3.3V ICS8745BYREV. C OCTOBER 27, 2008 ...
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... ICS8745B 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Schematic Example The schematic of the ICS8745B layout example is shown in Figure 5A. The ICS8745B recommended PCB board layout for this example is shown in Figure 5B. This layout example is used as a VDD RU2 RU3 RU4 RU5 RU6 ...
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... C6 U1 Pin 1 C1 Figure 5B. PCB Board Layout for ICS8745B IDT™ / ICS™ LVDS ZERO DELAY CLOCK GENERATOR and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. ...
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... Power Dissipation. The total power dissipation for the ICS8745B is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for V NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. ...
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... Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. Transistor Count The transistor count for ICS8745B is: 2772 IDT™ / ICS™ LVDS ZERO DELAY CLOCK GENERATOR θ vs. Air Flow ...
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... JEDEC Variation: BBC - HD All Dimensions in Millimeters Symbol Minimum Nominal 0.05 0.10 A2 1.35 1.40 b 0.30 0.37 c 0.09 D & E 9.00 Basic D1 & E1 7.00 Basic D2 & E2 5.60 Ref. e 0.80 Basic L 0.45 0.60 θ 0° ccc Reference Document: JEDEC Publication 95, MS-026 IDT™ / ICS™ LVDS ZERO DELAY CLOCK GENERATOR Maximum 1.60 0.15 1.45 0.45 0.20 0.75 7° 0.10 17 ICS8745BYREV. C OCTOBER 27, 2008 ...
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... Package Shipping Packaging 32 Lead LQFP 32 Lead LQFP 1000 Tape & Reel “Lead-Free” 32 Lead LQFP “Lead-Free” 32 Lead LQFP 1000 Tape & Reel 18 Temperature Tray 0°C to 70°C 0°C to 70°C Tray 0°C to 70°C 0°C to 70°C ICS8745BYREV. C OCTOBER 27, 2008 ...
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... T9 14 Ordering Information Table - added Lead-Free note Characteristics Table - changed Added Power Considerations section. Updated format throughout the datasheet. IDT™ / ICS™ LVDS ZERO DELAY CLOCK GENERATOR Description of Change max limit from 3.7ns to 4.0ns. PD ICS8745BYREV. C OCTOBER 27, 2008 19 Date 3/17/04 12/2/04 3/18/05 4/16/07 ...
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... ICS8745B 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) © ...