ics8745b Integrated Device Technology, ics8745b Datasheet - Page 12

• Manufacturer Part Number: ics8745b
• Description: 1 5 Differential-to-lvds Zero Delay Clock Generator
• Manufacturer: Integrated Device Technology

Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
CLK/CLK I
For applications not requiring the use of the differential input, both
CLK and CLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to
ground.
3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS drivers require a
matched load termination of 100Ω across near the receiver input.
Figure 4. Typical LVDS Driver Termination
IDT™ / ICS™ LVDS ZERO DELAY CLOCK GENERATOR
ICS8745B
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
3.3V
LVDS Driver
100Ω Differential Transmission Line
NPUT
:
50Ω
50Ω
R1
100Ω
12
Outputs:
LVDS Output
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, we
recommend that there is no trace attached.
For a multiple LVDS outputs buffer, if only partial outputs are used,
it is recommended to terminate the unused outputs.
+
–
3.3V
ICS8745BYREV. C OCTOBER 27, 2008