ics8745b Integrated Device Technology, ics8745b Datasheet - Page 13

• Manufacturer Part Number: ics8745b
• Description: 1 5 Differential-to-lvds Zero Delay Clock Generator
• Manufacturer: Integrated Device Technology

Schematic Example
The schematic of the ICS8745B layout example is shown in Figure
5A. The ICS8745B recommended PCB board layout for this
example is shown in Figure 5B. This layout example is used as a
Figure 5A. ICS8745B LVDS Zero Delay Buffer Schematic Example
IDT™ / ICS™ LVDS ZERO DELAY CLOCK GENERATOR
ICS8745B
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
3.3V
VDD
RU2
SP
RD2
1K
3.3V PECL Driver
RU3
1K
RD3
SP
RU4
1K
RD4
SP
Zo = 50 Ohm
Zo = 50 Ohm
(155.5 MHz)
RU5
SP
RD5
1K
RU6
1K
RD6
SP
R8A
50
R10
50
RU7
SP
RD7
1K
R9
50
SEL0
SEL1
SEL2
SEL3
PLL_SEL
CLK_SEL
SP = Space (i.e. not intstalled)
CLK_SEL
SEL0
SEL1
SEL2
VDD
8745
1
2
3
4
5
6
7
8
U3
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
VDDA
R2
100
13
0.01u
C11
VDDO
VDDO
general guideline. The layout in the actual system will depend on
the selected component types, the density of the components, the
density of the traces, and the stack up of the P.C. board.
GND
nQ3
nQ2
nQ1
Q3
Q2
Q1
(U1-9)
24
23
22
21
20
19
18
17
10u
C16
10
R7
(77.76 MHz)
0.1uF
C1
VDD
Decoupling capacitor located near the power pins
VDD
(U1-32)
0.1uF
C6
Zo = 50 Ohm
Zo = 50 Ohm
(U1-22)
0.1uF
C4
ICS8745BYREV. C OCTOBER 27, 2008
VDDO
R4
100
VDD=3.3V
VDDO=3.3V
SEL[3:0] = 0101,
Divide by 2
(U1-28)
+
-
0.1uF
C5
LVDS_input
(U1-16)
0.1uF
C2