ics8745b-21 Integrated Device Technology, ics8745b-21 Datasheet - Page 10

• Manufacturer Part Number: ics8745b-21
• Description: 1 1 Differential-to-lvds Zero Delay Clock Generator
• Manufacturer: Integrated Device Technology

Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. The ICS8745B-21 provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. V
connected to the power supply plane through vias, and bypass
capacitors should be used for each pin. To achieve optimum jitter
performance, power supply isolation is required. Figure 1
illustrates how a 10Ω resistor along with a 10μF and a .01μF
bypass capacitor should be connected to each V
resistor can also be replaced by a ferrite bead.
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
R2/R1 = 0.609.
IDT™ / ICS™ LVDS ZERO DELAY CLOCK GENERATOR
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
DD,
DD
V
DDA
= 3.3V, V_REF should be 1.25V and
and V
DDO
should be individually
DDA
pin. The 10Ω
DD
/2 is
10
Figure 2. Single-Ended Signal Driving Differential Input
Single Ended Clock Input
Figure 1. Power Supply Filtering
C1
0.1u
V
V
DDA
V_REF
DD
ICS8745BM-21REV. C OCTOBER 27, 2008
.01µF
.01µF
3.3V
R1
1K
R2
1K
10Ω
10µF
V
DD
CLK
nCLK