ics8745b-21 Integrated Device Technology, ics8745b-21 Datasheet - Page 2

• Manufacturer Part Number: ics8745b-21
• Description: 1 1 Differential-to-lvds Zero Delay Clock Generator
• Manufacturer: Integrated Device Technology

Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
IDT™ / ICS™ LVDS ZERO DELAY CLOCK GENERATOR
Symbol
C
R
R
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
IN
PULLUP
PULLDOWN
Number
19, 20
10, 14
12, 13
6, 15,
7, 11
8, 9
16
17
18
1
2
3
4
5
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
SEL2, SEL3,
SEL0 SEL1
QFB/QFB
PLL_SEL
Name
V
V
FBIN
FBIN
GND
CLK
CLK
Q/Q
V
MR
DDO
DDA
DD
Output
Output
Power
Power
Power
Power
Input
Input
Input
Input
Input
Input
Input
Type
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
Pullup
Pullup
Test Conditions
Description
Non-inverting differential clock input.
Inverting differential clock input.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true output Q to go low and the inverted output Q to go high. When
logic LOW, the internal dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
Inverting differential feedback input to phase detector for regenerating clocks
with “Zero Delay.”
Non-inverted differential feedback input to phase detector for regenerating
clocks with “Zero Delay.”
Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Output supply pins.
Differential feedback output pair. LVDS interface levels.
Power supply ground.
Differential output pair. LVDS interface levels.
Analog supply pin.
PLL select. Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects reference clock.
LVCMOS/LVTTL interface levels.
Core supply pin.
2
Minimum
ICS8745BM-21REV. C OCTOBER 27, 2008
Typical
51
51
4
Maximum
Units
k
k
pF
Ω
Ω