ics8745b-21 Integrated Device Technology, ics8745b-21 Datasheet - Page 11

• Manufacturer Part Number: ics8745b-21
• Description: 1 1 Differential-to-lvds Zero Delay Clock Generator
• Manufacturer: Integrated Device Technology

Differential Clock Input Interface
The CLK /CLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and
other differential signals. Both signals must meet the V
V
examples for the HiPerClockS CLK/CLK input driven by the most
common driver types. The input interfaces suggested here are
Figure 3A. HiPerClockS CLK/CLK Input Driven by an
Figure 3C. HiPerClockS CLK/CLK Input
IDT™ / ICS™ LVDS ZERO DELAY CLOCK GENERATOR
CMR
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
input requirements. Figures 3A to 3D show interface
1.8V
3.3V
LVPECL
LVHSTL
IDT
HiPerClockS
LVHSTL Driver
IDT HiPerClockS LVHSTLDriver
Driven by a 3.3V LVPECL Driver
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
R3
125
R1
50
3.3V
R1
84
R4
125
R2
50
R2
84
CLK
nCLK
CLK
nCLK
3.3V
3.3V
HiPerClockS
Input
HiPerClockS
Input
PP
and
11
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 3A, the input termination applies for IDT
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
Figure 3B. HiPerClockS CLK/CLK Input
Figure 3D. HiPerClockS CLK/CLK Input Driven by
3.3V
3.3V
LVDS
LVPECL
Driven by a 3.3V LVPECL Driver
a 3.3V LVDS Driver
Zo = 50Ω
Zo = 50Ω
ICS8745BM-21REV. C OCTOBER 27, 2008
Zo = 50Ω
Zo = 50Ω
R1
50
R2
50
R2
50
R1
100
CLK
nCLK
CLK
nCLK
3.3V
3.3V
HiPerClockS
Input
Receiver