ics9248-136 Integrated Device Technology, ics9248-136 Datasheet
ics9248-136
Related parts for ics9248-136
ics9248-136 Summary of contents
Page 1
... ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. ICS9248-136 Advance Information Pin Configuration 1 48 VDDCPU 2 47 CPUCLKT0 3 ...
Page 2
... ICS9248-136 Advance Information Pin Configuration PIN NUMBER PIN NAME 1, 7, 15, 22, 25, VDD 35, 43, 48 AGPSEL 2 REF1 FS3 3 REF0 4, 14, 18, 19, 29, GND 32, 39 FS1 8 PCICLK_F FS2 9 PCICLK0 13, 12, 11, 10 PCICLK (4:1) 17, 16 AGPCLK (1:0) FS0 20 48MHz M ODE 21 24_48M Hz 23 SDATA 24 SCLK CPU_STOP# 27 SDRAM 11 ...
Page 3
... General Description The ICS9248-136 is the single chip clock solution for Desktop/Notebook designs using the SIS 630S style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-136 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations ...
Page 4
... ICS9248-136 Advance Information Serial Configuration Command Bitmap Byte0: Functionality and Frequency Select Register (default = ...
Page 5
... ICS9248-136 Advance Information ...
Page 6
... ICS9248-136 Advance Information Byte 6: Control , Active/Inactive Register (1= enable disable ...
Page 7
... CONDITIONS pF; Select @ 66M 3 Logic Inputs X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From target Freq 1 1 ICS9248-136 Advance Information +0 TYP -0.3 0.8 SS 180 1.0 4.0 500.0 UNITS +0 ...
Page 8
... ICS9248-136 Advance Information Electrical Characteristics - CPUCLK (Open Drain 70º 3.3 V +/-5 PARAMETER SYMBOL Output Impedance Z O Output High Voltage V OH2B Output Low Voltage V OL2B Output Low Current I OL2B 1 t Rise Time r2B 1 t Fall Time f2B 1 V Differential voltage-AC ...
Page 9
... c-cyc T 9 ICS9248-136 Advance Information M IN TYP M AX UNITS 2.4 V 0 2.0 ns 2.0 ns 45.0 55.0 % 250 ps 150 TYP M AX UNITS 10 20 ...
Page 10
... ICS9248-136 Advance Information General I The information in this section assumes familiarity with I For more information, contact ICS for an I How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends a dummy command code • ...
Page 11
... The programming resistors should be located close to the series termination resistor to minimize the current loop area more important to locate the series termination resistor close to the driver than the programming resistor. Via to VDD 2K 8.2K Clock trace to load Series Term. Res. Fig ICS9248-136 Advance Information ...
Page 12
... CPU_STOP asychronous input to the clock synthesizer used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9248-136. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse ...
Page 13
... PCI_STOP# Timing Diagram PCI_STOP asynchronous input to the ICS9248-136 used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-136 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed ...
Page 14
... SDRAM_STOP asychronous input to the clock synthesizer used to stop SDRAM clocks for low power operation. SDRAM_STOP# is synchronized to complete it's current cycle, by the ICS9248-136. All other clocks will continue to run while the SDRAM clocks are disabled. The SDRAM clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse ...
Page 15
... Crystal Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-136 device shown, the outputs Stop Low on the next falling edge after PD# goes low asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. ...
Page 16
... ICS9248-136 Advance Information Ordering Information ICS9248yF-136-T Example: ICS XXXX PPP - T Third party brands and names are the property of their respective owners. SYMBOL VARIATIONS Designation for tape and reel packaging Pattern Number ( digit number for parts with ROM code patterns) ...