ics9248-95 Integrated Device Technology, ics9248-95 Datasheet
ics9248-95
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ics9248-95 Summary of contents
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... Circuit Systems, Inc. Frequency Generator & Integrated Buffers for PENTIUM/Pro General Description The ICS9248-95 is the single chip clock solution for Desktop designs using the VIA MVP4 style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I Spread spectrum typically reduces system EMI by 8dB to 10dB ...
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... ICS9248-95 Pin Descriptions ...
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... ICS9248-95 ...
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... ICS9248-95 General I The information in this section assumes familiarity with I How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends a dummy command code • ICS clock will acknowledge • ...
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... ICS9248- ...
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... ICS9248-95 Byte 1: CPU, Active/Inactive Register (1 = enable disable ...
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... ICS9248-95 ...
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... CLK_STOP asychronous input to the clock synthesizer used to turn off the CPU clocks for low power operation. CLK_STOP# is synchronized by the ICS9248-95. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse ...
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... PCI_STOP# Timing Diagram PCI_STOP asynchronous input to the ICS9248-95 used to turn off the PCICLK [4:0] clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-95 internally. The minimum that the PCICLK [4:0] clocks are enabled (PCI_STOP# high pulse least 10 PCICLK [4:0] clocks. PCICLK [4:0] clocks are stopped in a low state and started with a full high pulse width guaranteed ...
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... ICS9248-95 Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) on the ICS9248- 95 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function ...
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... Fig. 2a Fig ICS9248-95 ...
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... ICS9248-95 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0 Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied ...
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... V *(0. *( ICS9248-95 MIN TYP MAX UNITS Ω Ω 2.3 V 0.2 0.4 V -41 - 0.4 2.0 nS 0.4 1.0 2.0 nS 45.0 51.0 55.0 % 120 250 pS 250 300 pS 150 pS 208 ...
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... ICS9248-95 Electrical Characteristics - PCI 70C 3.3 V +/-5 PARAMETER SYMBOL 1 Output Impedance R DSP1 1 Output Impedance R DSN1 Output High Voltage V OH1 Output Low Voltage V OL1 Output High Current I OH1 Output Low Current I OL1 1 Rise Time Fall Time Duty Cycle ...
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... Annealed Lead Free (optional) Pattern Number ( digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator Device Type (consists digit numbers) Prefix ICS Standard Device 15 ICS9248- ...
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... ICS9248-95 Revision History Rev. Issue Date Description C 4/4/2005 1. Updated CPU,PCI, and SDRAM Electrical Characteristics. 1. Updated Electrical Characteristics for Input/Output Parameters, CPU and SDRAM. 2. Added Lead Free option. D 4/12/2005 3. Datasheet Release. 310D—04/12/05 16 Page # 13-14 12-15 ...