ics1893ck-40 Integrated Device Technology, ics1893ck-40 Datasheet
ics1893ck-40
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ics1893ck-40 Summary of contents
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... Station-Management (STA) entity. The ICS1893CK-40 Media-Dependent Interface (MDI) can be configured to provide either half- or full-duplex operation at data rates of 10 Mb/s or 100Mb/s. The ICS1893CK-40 is available in a 6mm x 6mm 40-lead MLF package. Applications: NIC cards, PC motherboards, switches, routers, DSL and cable modems, game machines, printers, network connected appliances, and industrial equipment ...
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... ICS1893CK-40 Data Sheet - Release Revision History • Initial preliminary release of this document, Rev. A, dated October 2, 2007. • Rev B; removed all references to CRS and COL; removed AMDIX_EN (pin 10) and all references. • Rev C; updated hex numerology in table 7-9. • ICS1893CK-40, Rev. C, 06/02/09 Copyright © 2009, Integrated Device Technology, Inc. ...
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... ICS1893CK-40 Data Sheet Rev Release Chapter 1 Abbreviations and Acronyms Table 1-1 lists and interprets the abbreviations and acronyms used throughout this data sheet. Table 1-1. Abbreviations and Acronyms Abbreviation / Acronym 4B/5B 4-Bit / 5-Bit Encoding/Decoding ANSI American National Standards Institute CMOS complimentary metal-oxide semiconductor CSMA/CD ...
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... Open Systems Interconnection OUI Organizationally Unique Identifier PCS Physical Coding sublayer PHY physical-layer device The ICS1893CK- physical-layer device, also referred ‘PHY’ or ‘PHYceiver’. (The ICS1890 is also a physical-layer device.) PLL phase-locked loop PMA Physical Medium Attachment PMD Physical Medium Dependent ...
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... A pin name that includes a forward slash ‘/’ multi-function, configuration pin. These pins provide the ability to select between two ICS1893CK-40 functions. The name provided: – Before the ‘/’ indicates the pin name and function when the signal level on the pin is logic zero. – ...
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... The terms ‘cleared’, ‘inactive’, and ‘de-asserted’ are synonymous. They do not necessarily infer logic zero. In reference to the ICS1893CK-40, the term ‘Twisted-Pair Receiver’ refers to the set of Twisted-Pair Receive output pins (TP_RXP and TP_RXN). In reference to the ICS1893CK-40, the term ‘Twisted-Pair Transmitter’ refers to the set of Twisted-Pair Transmit output pins (TP_TXP and TP_TXN). Copyright © ...
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... Physical Medium Dependent sublayer (PMD) • Auto-Negotiation sublayer The ICS1893CK-40 is transparent to the next layer of the OSI model, the link layer. The link layer has two sublayers: the Logical Link Control sublayer and the MAC sublayer. The ICS1893CK-40 can interface directly to the MAC. ...
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... Start-of-Stream Delimiters (SSDs) and End-of-Stream Delimiters (ESDs) into the data stream. The ICS1893CK-40 encapsulates each MAC frame, including the preamble, with an SSD and an ESD. As per the ISO/IEC Standard, the ICS1893CK-40 replaces the first octet of each MAC preamble with an SSD and appends an ESD to the end of each MAC frame. ...
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... The ICS1893CK-40 register bits are accessible through a standard MII (Media Independent Interface) Serial Management Port. The ICS1893CK-40 is configured to support the MAC Interface as a 10M MII or a 100M MII. The protocol on the Medium Dependent Interface (MDI) can be configured to support either 10M or 100M operations in either half-duplex or full-duplex modes ...
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... Releases all MAC Interface pins, which takes a maximum of 640 ns after the reset condition is removed 4.1.1.3 Hot Insertion As with the ICS189X products, the ICS1893CK-40 reset design supports ‘hot insertion’ of its MII. (That is, the ICS1893CK-40 can connect its MAC Interface to a MAC while power is already applied to the MAC.) ICS1893CK-40, Rev. C, 06/02/09 Operations”. ...
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... Section 4.1.1.1, “Entering Exiting Hardware Reset After the signal on the RESETn pin transitions from a low to a high state, the ICS1893CK-40 completes in 640 ns (that is REF_IN clocks) steps 1 through 5, listed in first five steps are completed, the Serial Management Port is ready for normal operations, but this action does not signify the end of the reset cycle ...
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... LL, LH, and LMX Management Register bits are re-initialized to their default values. • During a reset, the ICS1893CK-40 sets all of its Management Register bits to their default values. It does not maintain the state of any Management Register bit. For more information on power-down operations, see the following: • ...
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... ICS1893CK-40 is operating in 10Base-T mode. 4.4 Auto-Negotiation Operations The ICS1893CK-40 has an Auto-Negotiation sublayer and provides a Control Register bit (bit 0.12) to determine whether its Auto-Negotiation sublayer is enabled or disabled. When enabled, the ICS1893CK-40 Auto-Negotiation sublayer exchanges technology capability data with its remote link partner and automatically selects the highest-performance operating mode it has in common with its remote link partner. For example, if the ICS1893CK-40 supports 100Base-TX and 10Base-T modes – ...
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... Operations The ICS1893CK-40 10Base-T mode provides 10Base-T physical layer (PHY) services as defined in the ISO/IEC 8802-3 standard. In the 10Base-T mode, the ICS1893CK- 10M translator between a MAC and the physical transmission medium. In 10Base-T mode, the ICS1893CK-40 provides the following functions: • ...
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... ICS1893CK-40 Data Sheet Rev Release 4.8 Auto-MDI/MDIX Crossover (New) The ICS1893CK-40 includes the auto-MDI/MDIX crossover feature typical CAT 5 Ethernet installation the transmit twisted pair signal pins of the RJ45 connector are crossed over in the CAT 5 wiring to the partners receive twisted pair signal pins and receive twisted pair to the partners transmit twisted pair. This is usually accomplished in the wiring plant ...
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... ICS1893CK-40 Data Sheet - Release Chapter 5 Interface Overviews The ICS1893CK-40 MAC Interface is fully configurable, thereby allowing it to accommodate many different applications. This chapter includes overviews of the following MAC-to-PHY interfaces: • Section 5.1, “MII Data Interface” • Section 5.2, “Serial Management Interface” ...
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... The ICS1893CK-40’s MAC Interface is the Media Independent Interface (MII) operating at either 10 Mbps or 100 Mbps. The ICS1893CK-40 MAC Interface is configured for the MII Data Interface mode, data is transferred between the PHY and the MAC as framed, 4-bit parallel nibbles. In addition, the interface also provides status and control signals to synchronize the transfers ...
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... ICS1893CK-40. The ISO/IEC standard also specifies a frame structure and protocol for this interface as well as a set of Management Registers that provide the STA with access to a PHY such as the ICS1893CK-40. A Serial Management Interface is comprised of two signals: a bi-directional data pin (MDIO) along with an associated input pin for a clock (MDC) ...
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... ICS1893CK-40 Data Sheet Rev Release Figure 5-1. ICS1893CK-40 Twisted Pair * TP_AP 12 ICS1893CK TP_AN 13 Ideally, for these traces Z TP_BP 16 TP_BN 15 Ideally, for these traces Z * For backward compatibility, refer to the the “1893C Alternate Schematic” application note. ICS1893CK-40, Rev. C, 06/02/09 System Ground Plane 1:1 49.9Ω 1% Center ...
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... MHz ±50 parts per million. This accuracy is necessary to meet the interface requirements of the ISO/IEEE 8802-3 standard, specifically clauses 22.2.2.1 and 24.2.3.4. The ICS1893CK-40 supports two clock source configurations: a CMOS oscillator or a CMOS driver. The input to REF_IN is CMOS (10% to 90% VDD), not TTL. Alternately, a 25MHz crystal may be used. The Oscillator specifications are shown in Table 5 ...
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... If a crystal is used as the clocking source, connect it to both the Ref_in (pin 47) and Ref_out (pin 46) pins of the ICS1893CK-40. A pair of bypass capacitors on either side of the crystal are connected to ground. The crystal is used in the parallel resonance or anti-resonance mode. The value of the load caps serve to adjust the final frequency of the crystal oscillation ...
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... A software reset does not affect the state of a multi-function configuration pin. During a software reset, all multi-function configuration pins are outputs. 3. Each multi-function configuration pin must be pulled either up or down with a resistor to establish the address of the ICS1893CK-40. LEDs may be placed in series with these resistors to provide a designated status indicator as described in Table 5-3. Use 1KΩ resistors. Caution: All pins listed in Table 5-3 must not float ...
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... ICS1893CK-40 Data Sheet Rev Release Figure 5-3 shows typical biasing and LED connections for the ICS1893CK-40. Figure 5-3. ICS1893CK-40 LED - PHY Interface P4RD P3TD 8 6 REC 10KΩ 10KΩ This circuit decodes to PHY address = 1. Notes: 1. All LED pins must be set during reset. ...
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... ICS1893CK-40 Data Sheet - Release Chapter 6 Functional Blocks This chapter discusses the following ICS1893CK-40 functional blocks. • Section 6.1, “Functional Block: Media Independent Interface” • Section 6.2, “Functional Block: Auto-Negotiation” • Section 6.3, “Functional Block: 100Base-X PCS and PMA Sublayers” • Section 6.4, “Functional Block: 100Base-TX TP-PMD Operations” ...
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... Functional Block: Media Independent Interface All ICS1893CK-40 MII interface signals are fully compliant with the ISO/IEC 8802-3 standard. In addition, the ICS1893CK-40 MIIs can support two data transfer rates: 25 MHz (for 100Base-TX operations) and 2.5 MHz (for 10Base-T operations). The Media Independent Interface (MII) consists of two primary components: 1 ...
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... The ICS1893CK-40 obtains the data for its FLP bursts from the Auto-Negotiation Advertisement Register (Register 4). 3. Both the ICS1893CK-40 and the remote link partner substitute Fast Link Pulse (FLP) bursts in place of the Normal Link Pulses (NLPs). In each FLP burst, the ICS1893CK-40 transmits information on its technology capability through its Link Control Word, which includes link configuration and status data ...
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... If the remote link partner responds to the FLP bursts with FLP bursts, then the link partner is a 100Base-TX node that can support the auto-negotiation process. In this case, the ICS1893CK-40 sets to logic one the Auto-Negotiation Expansion Register’s Link Partner Auto-Negotiation Ability bit (bit 6.0). ...
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... ICS1893CK-40 Data Sheet - Release 6.2.3 Auto-Negotiation: Remote Fault Signaling If the remote link partner detects a fault, the ICS1893CK-40 reports the remotely detected fault to the STA by setting to logic one the Remote Fault Detected bit(s), 1.4, 5.13, 17.1, and 19.13. In general, the reception of a remote fault means that the remote link partner has a problem with the integrity of its receive channel ...
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... Physical Coding sublayer (PCS) and Physical Medium Attachment (PMA) sublayers. 6.3.1 PCS Sublayer The ICS1893CK-40 100Base-X PCS sublayer provides two interfaces: one to a MAC and the other to the ICS1893CK-40 PMA sublayer. An ICS1893’s PCS sublayer performs the transmit, receive, and control functions and consists of the following: • ...
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... Both the PCS and PMA sublayers have Receive modules. 6.3.4.1 PCS Receive Module The ICS1893CK-40 PCS Receive module accepts both a serial bit stream and a clock signal from the PMA sublayer. The PCS Receive module converts the bit stream from a serial format to a parallel format and then processes the data to detect the presence of a carrier ...
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... MAC Interface. Detection of an error forces the Receive state machine to assert the receive error signal (RX_ER) and wait for the next symbol. If the ICS1893CK-40 Receive state machine detects a premature end, it forces the assertion of the RX_ER signal, sets the Premature End bit (bit 17.5) to logic one, and transitions to the IDLE State ...
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... A Halt symbol, it sets the Halt Symbol Detected bit in its QuickPoll Detailed Status Register (bit 17.6) to logic one. Note: An STA can force the ICS1893CK-40 to transmit symbols that are typically classified as invalid, by both (1) setting the Extended Control Register’s Transmit Invalid Codes bit (bit 16.2) to logic one and (2) asserting the associated TXER signal. For more information, see Error Code Test (bit 6 ...
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... Baseline wander adversely affects the noise immunity of the receiver, because the ‘baseline’ signal moves or ‘wanders’ from its nominal DC value. The ICS1893CK-40 uses a unique technique to restore the DC component ‘lost’ by the medium result, the design is very robust, immune to noise and independent of the data stream ...
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... Manchester- encoded, 10Base-T signal from the isolation transformer). Note reference to the ICS1893CK-40, the term ‘Twisted-Pair Receiver’ refers to the set of Twisted-Pair Receive output pins (TP_RXP and TP_RXN). 2. For information on the 10Base-T Twisted-Pair Receiver, see Twisted-Pair Receiver” ...
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... MAC Frame Preamble and continue as long as the ICS1893CK-40 is receiving data. 6.5.4 10Base-T Operation: Idle An ICS1893CK-40 transmits Normal Link Pulses on its MDI in the absence of data. During this time the link is Idle, and the ICS1893CK-40 periodically transmits link pulses at a rate of one link pulse every compliance with the ISO/IEC 8802-3 standard ...
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... When a link is invalid and the Link Monitor Function detects the presence of data, the ICS1893CK-40 does not transition the link to the valid state until after the reception of the present packet is complete. ...
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... When enabled, the ICS1893CK-40 performs the SQE Test at the completion of each transmitted packet (that is, whenever its TX_EN signal transitions from asserted to de-asserted). When the ICS1893CK-40 executes its SQE Test, it asserts the COL signal to its MAC Interface for a pre-determined time duration (ISO/IEC specified). [For more information, see Heartbeat Timing (SQE)” ...
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... The ICS1893CK-40 accomplishes reversed signal polarity detection and correction by examining the signal polarity of the Normal Link Pulses (NLPs). In 10Base-T mode, an ICS1893CK-40 transmits and receives NLPs when its link is in the Idle state. In 100Base-TX mode, an ICS1893CK-40 transmits and receives NLPs during Auto-Negotiation. An STA can control this feature using the 10Base-T Operations Register bit 18.3, the Auto Polarity-Inhibit bit. When this bit is logic: • ...
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... In compliance with the ISO/IEC specification, the ICS1893CK-40 implementation of the serial management interface provides a bi-directional data pin (MDIO) along with a clock (MDC) for synchronizing the exchange of data. These pins remain active in all ICS1893CK-40 MAC Interface modes (that is, the 10/100 MII, 100M Symbol, and 10M Serial interface modes). ...
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... A valid Management Frame includes an operation code (OP) immediately following the start-of-frame delimiter. There are two valid operation codes: one for reading from a management register, 10b, and one for writing to a management register, 01b. The ICS1893CK-40 does not respond to the codes 00b and 11b, which the ISO/IEC specification defines as invalid. ...
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... Read, an ICS1893CK-40 remains in the high-impedance state during the first bit time and subsequently drives its MDIO pin to logic zero for the second bit time. • Write, an ICS1893CK-40 waits while the STA transmits a logic one, followed by a logic zero on its MDIO pin. 6.6.2.8 Management Frame Data A valid management frame includes a 16-bit Data field for exchanging the register contents between the ICS1893CK-40 and the STA ...
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... ICS1893CK-40 Data Sheet - Release Chapter 7 Management Register Set The tables in this chapter detail the functionality of the bits in the management register set. The tables include the register locations, the bit positions, the bit definitions, the STA Read/Write Access Types, the default bit values, and any special bit functions or capabilities (such as self-clearing). Following each table is a description of each bit. This chapter includes the following sections: • ...
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... Reserved by IEEE 16 through 31 Vendor-Specific (IDT) Registers Table 7-2 lists the IDT-specific registers that the ICS1893CK-40 implements. These registers enhance the performance of the ICS1893CK-40 and provide the Station Management entity (STA) with additional control and status capabilities. Table 7-2. IDT-Specific Registers Register Address 16 Extended Control ...
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... Read/Write Read/Write Zero 7.1.3 Management Register Bit Default Values The tables in this chapter specify for each register bit the default value, if one exists. The ICS1893CK-40 sets all Management Register bits to their default values after a reset. for ICS1893CK-40 Management Register bits. Table 7-4. Range of Possible Valid Default Values for ICS1893CK-40 Register Bits Default Condition – ...
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... LMX bits retain their value until either a reset occurs or they are read by an STA. Immediately following an STA read of a defined group of LMX bits, the ICS1893CK-40 latches the current state of the monitored state machine into the LMX bits. When an STA reads a group of LMX bits: • ...
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... Reserved bits. 7.2.1 Reset (bit 0.15) This bit controls the software reset function. Setting this bit to logic one initiates an ICS1893CK-40 software reset during which all Management Registers are set to their default values and all internal state machines are set to their idle state. For a detailed description of the software reset process, see “ ...
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... Bit 0.12 determines whether to enable the Auto-Negotiation sublayer. When bit 0.12 is logic: – Zero: • The ICS1893CK-40 disables the Auto-Negotiation sublayer. • The ICS1893CK-40 bit 0.13 (the Data Rate bit) and bit 0.8 (the Duplex Mode bit) determine the data rate and the duplex mode. – One: • ...
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... Is equal to 00000b, then the default value of bit 0.10 is logic one, and the ICS1893CK-40 isolates itself from the MAC Interface. • Is not equal to 00000b, then the default value of bit 0.10 is logic zero, and the ICS1893CK-40 does not isolate its MAC Interface. 7.2.7 Restart Auto-Negotiation (bit 0.9) This bit allows an STA to restart the auto-negotiation process in Software mode (that is, the HW/SW pin is logic one) ...
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... One, as per the ISO/IEE 8802-3 standard, clause 22.2.4.1.9, the ICS1893CK-40 enables the collision detection circuitry for the Collision Test function, even if the ICS1893CK- Loopback mode (that is, bit 0.14 is set to 1). In this case, the Collision Test function tracks the Collision Detect signal (COL) in response to the TXEN signal ...
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... Table 7-6 lists the Status Register bits. These 16 bits of data provide an interface between the ICS1893CK-40 and an STA. There are two types of status bits: some report the capabilities of the port, and some indicate the state of signals used to monitor internal circuits. The STA accesses the Status Register using the Serial Management Interface. During a reset, the ICS1893CK-40 initializes the Status Register bits to pre-defined, default values ...
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... Therefore, when an STA reads the Status Register, the STA is informed that the ICS1893CK-40 supports 10Base-T, half-duplex operations.) Bit 1.11 of the ICS1893CK-40 Status Register is a Command Override Write bit., which allows an STA to alter the default value of this bit. [See the description of bit 16.15, the Command Override Write Enable bit, in Section 7.11, “ ...
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... This default value ensures that bit 1.6 is backward compatible with the ICS1890, which does not have this capability. As the means of enabling this feature, the ICS1893CK-40 implements bit 1 Command Override Write bit, instead Read-Only bit as in the ICS1890. An STA uses the bit 1.6 to enable MF Preamble Suppression in the ICS1893CK-40 ...
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... ICS1893CK-40 Data Sheet Rev Release 7.3.9 Remote Fault (bit 1.4) An STA reads bit 1.4 to determine if a Remote Fault exists. The ICS1893CK-40 sets bit 1.4 based on the Remote Fault bit received from its remote link partner. The ICS1893CK-40 receives the Remote Fault bit as part of the Link Code Word exchanged during the auto-negotiation process. If the ICS1893CK-40 receives a Link Code Word from its remote link partner and the Remote Fault bit is set to: • ...
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... ICS1893CK-40 Data Sheet - Release 7.3.12 Jabber Detect (bit 1.1) The purpose of this bit is to allow an STA to determine if the ICS1893CK-40 detects a Jabber condition as defined in the ISO/IEC specification.The ICS1893CK-40 Jabber Detection function is controlled by the Jabber Inhibit bit in the 10Base-T Operations register (bit 18.5). To detect a Jabber condition, first the ICS1893CK-40 Jabber Detection function must be enabled. When bit 18.5 is logic: • ...
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... ICS1893CK-40 Data Sheet Rev Release 7.4 Register 2: PHY Identifier Register Table 7-7 lists the bits for PHY Identifier Register (Register 2), which is one of two PHY Identifier Registers that are part of a set defined by the ISO/IEC specification set, the PHY Identifier Registers (Registers 2 and 3) include a unique, 32-bit PHY Identifier composed from the following: • ...
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... ICS1893CK-40 Data Sheet - Release IEEE-Assigned Organizationally Unique Identifier (OUI) For each manufacturing organization, the IEEE assigns an 3-octet OUI. For Integrated Circuit Systems, Inc. the IEEE-assigned 3-octet OUI is 00A0BEh. This OUI is retained for backwards compatibility with older versions of the ICS1893. The binary representation of an OUI is formed by expressing each octet as a sequence of eight bits, from least significant to most significant, and from left to right ...
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... The most-significant 6 bits of register 3 (that is, bits 3.15:10) include OUI bits 19 through 24. OUI bit 19 is stored in bit 3.15, while OUI bit 24 is stored in bit 3.10. 7.5.2 Manufacturer's Model Number (bits 3.9:4) The model number for the ICS1893CK- (decimal stored in bit 3.9:4 as 00101b. 7.5.3 Revision Number (bits 3.3:0) Table 7-10 lists the valid ICS1893CK-40 revision numbers, which are 4-bit binary numbers stored in bits 3 ...
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... If bit 4.15 is logic: • Zero, then the ICS1893CK-40 indicates to its remote link partner that these features are disabled. (Although the default value of this bit is logic zero, the ICS1893CK-40 does support the Next Page function.) • One, then the ICS1893CK-40 advertises to its remote link partner that this feature is enabled. ...
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... Link Code Word that the ICS1893CK-40 exchanges with its remote link partner. The ICS1893CK-40 sets this bit to logic one whenever it detects a problem with the link, locally. The data in this register is sent to the remote link partner to inform it of the potential problem. If the ICS1893CK-40 does not detect a link fault, it clears bit 4.13 to logic zero. ...
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... ICS1893CK-40 to provide these technologies. Note: 1. The ICS1893CK-40 does not alter the value of the Status Register bits based on the TAF bits in register 4, as the ISO/IEC definitions for the Status Register bits require these bits to indicate all the capabilities of the ICS1893CK-40 ...
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... ICS1893CK-40 Data Sheet Rev Release auto-negotiation process. The ICS1893CK-40 supports IEEE Std. 802.3, represented by a value of 00001b in bits 4.4:0. The ISO/IEC 8802-3 standard defines the Selector Field technologies in Annex 28A. ICS1893CK-40, Rev. C, 06/02/09 Copyright © 2009, Integrated Device Technology, Inc. All rights reserved. ...
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... During the auto-negotiation process, the ICS1893CK-40 advertises (that is, exchanges) the capability data with its remote link partner using a pre-defined Link Code Word. The value of the Link Control Word received from its remote link partner establishes the value of the bits in this register ...
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... Zero, it indicates that the remote link partner has not received the ICS1893CK-40 Link Control Word. • One, it indicates to the ICS1893CK-40 / STA that the remote link partner has acknowledged reception of the ICS1893CK-40 Link Control Word. 7.7.3 Remote Fault (bit 5.13) The ISO/IEC specification defines bit 5.13 as the Remote Fault bit. This bit is set based on the Link Control Word received from the remote link partner. When this bit is a logic: • ...
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... Writes to a reserved bit, the STA must use the default value specified in this data sheet. ICS uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the ICS1893CK-40, an STA must maintain the default value of these bits. Therefore, IDT recommends that an STA always write the default value of any reserved bits during all management register write operations. ...
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... Next Page bit in its Link Control Word. 7.8.4 Next Page Able (bit 6.2) Bit 6 status bit that reports the capabilities of the ICS1893CK-40 to support the Next Page features of the auto-negotiation process. The ICS1893CK-40 sets this bit to a logic one to indicate that it can support these features ...
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... ICS1893CK-40 Data Sheet - Release 7.9 Register 7: Auto-Negotiation Next Page Transmit Register Table 7-14 lists the bits for the Auto-Negotiation Next Page Transmit Register, which establishes the contents of the Next Page Link Control Word that is transmitted during Next Page Operations. This table is compliant with the ISO/IEC specification. ...
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... Zero, it indicates that the ICS1893CK-40 cannot comply with the message. • One, it indicates to the remote link partner that the ICS1893CK-40 can comply with the message. 7.9.5 Toggle (bit 7.11) The Toggle (T) bit (bit 7.11) is used to synchronize the transmission of Next Page messages with the remote link partner ...
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... ICS1893CK-40 Data Sheet - Release 7.10 Register 8: Auto-Negotiation Next Page Link Partner Ability Register Table 7-15 lists the bits for the Auto-Negotiation Next Page Link Partner Ability Register, which establishes the contents of the Next Page Link Control Word that is transmitted during Next Page Operations. This table is compliant with the ISO/IEC specification ...
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... Zero, it indicates that the ICS1893CK-40 cannot comply with the message. • One, it indicates to the remote link partner that the ICS1893CK-40 can comply with the message. If the previous Next Page Link Control Word Toggle bit has a value of logic: • Zero, then the Toggle bit is set to logic one. ...
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... ICS1893CK-40 Data Sheet - Release 7.11 Register 16: Extended Control Register Table 7-16 lists the bits for the Extended Control Register, which the ICS1893CK-40 provides to allow an STA to customize the operations of the device. Note: 1. For an explanation of acronyms used in 2. During any write operation to any bit in this register, the STA must write the default value to all Reserved bits ...
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... Pins”). The PHY address is then latched into this register. (The value of each of the PHY Address bits is unaffected by a software reset.) 7.11.4 Stream Cipher Scrambler Test Mode (bit 16.5) The Stream Cipher Scrambler Test Mode bit is used to force the ICS1893CK-40 to lose LOCK, thereby requiring the Stream Cipher Scrambler to resynchronize. 7.11.5 ICS Reserved (bit 16.4) See Section 7.11.2, “ ...
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... ICS1893CK-40 Data Sheet - Release 7.11.7 Invalid Error Code Test (bit 16.2) The Invalid Error Code Test bit allows an STA to force the ICS1893CK-40 to transmit symbols that are typically classified as invalid. The purpose of this test bit is to permit thorough testing of the 4B/5B encoding and the serial transmit data stream by allowing generation of bit patterns that are considered invalid by the ISO/IEC 4B/5B definition ...
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... Note: 1. For an explanation of acronyms used in 2. Most of this register’s bits are latching high or latching low, which allows the ICS1893CK-40 to capture and save the occurrence of an event for an STA to read. (For more information on latching high and latching low bits, see Section 7.1.4.1, “ ...
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... When bit 17.14 is logic: • Zero, it indicates that half-duplex operations are selected. • One, the ICS1893CK-40 is indicating that full-duplex operations are selected. Note: This bit does not imply any link status. 7.12.3 Auto-Negotiation Progress Monitor (bits 17.13:11) The Auto-Negotiation Progress Monitor consists of the Auto-Negotiation Complete bit (bit 17.4) and the three Auto-Negotiation Monitor bits (bits 17 ...
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... This bit has no definition in 10Base-T mode. 7.12.5 100Base PLL Lock Error (bit 17.9) The Phase-Locked Loop (PLL) Lock Error bit indicates to an STA whether the ICS1893CK-40 has ever experienced a PLL Lock Error. A PLL Lock Error occurs when the PLL fails to lock onto the incoming 100Base data stream. If this bit is set to a logic: • ...
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... When the ICS1893CK-40 is receiving a packet, it examines each received Symbol to ensure the data is error free error occurs, the port indicates this condition to the MAC by asserting the RXER signal. In addition, the ICS1893CK-40 sets its Invalid Symbol bit to logic one. Therefore, if this bit is set to a logic: • ...
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... The Premature End bit indicates to an STA the detection of two consecutive Idles in a 100Base data stream by the ICS1893CK-40. During reception of a valid packet, the ICS1893CK-40 examines each symbol to ensure that the data being passed to the MAC Interface is error free. If two consecutive Idles are encountered, it indicates this condition to the MAC by setting this bit ...
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... Link Loss inhibit 18.0 Squelch inhibit 7.13.1 Remote Jabber Detect (bit 18.15) The Remote Jabber Detect bit is provided to indicate that an ICS1893CK-40 port has detected a Jabber Condition on its receive path. This bit is reset to logic zero on a read of the 10Base-T operations register. When this bit is logic: • ...
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... ICS1893CK-40 Data Sheet Rev Release 7.13.2 Polarity Reversed (bit 18.14) The Polarity Reversed bit is used to inform an STA whether the ICS1893CK-40 has detected that the signals on the Twisted-Pair Receive Pins (TP_RXP and TP_RXN) are reversed. When the signal polarity is: • Correct, the ICS1893CK-40 sets bit 18. logic zero. ...
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... This bit is a control bit and not a status bit. Therefore not updated to indicate this automatic inhibiting of the SQE test in full-duplex mode or repeater mode. 7.13.8 Link Loss Inhibit (bit 18.1) The Link Loss Inhibit bit allows an STA to prevent the ICS1893CK-40 from dropping the link in 10Base-T mode. When an STA sets this bit to logic: • ...
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... ICS1893CK-40 Data Sheet Rev Release 7.14 Register 19: Extended Control Register 2 The Extended Control Register provides more refined control of the internal ICS1893CK-40 operations. Note: 1. For an explanation of acronyms used in 2. During any write operation to any bit in this register, the STA must write the default value to all Reserved bits ...
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... Section 7.11.2, “ICS Reserved (bits 7.14.5 Auto-MDI/MDIX (bits 19. 9:8) (New) The ICS1893CK-40 includes the Auto-MDI/MDIX crossover feature. The Auto-MDI/MDIX feature automatically selects the correct MDI or MDIX configuration to match the cable plant by automatically swapping transmit and receive signal pairs at the PHY. Auto-MDI/MDIX is defaulted on but may be disabled for test purposes by writing (bits 19 ...
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... AMDIX_EN [19:9] MDI_MODE [19:8] MDIO register 13h bit 8 7.14.6 Twisted Pair Tri-State Enable, TPTRI (bit 19.7) The ICS1893CK-40 provides a Twisted Pair Tri-State Enable bit. This bit forces the TP_TXP and TP_TXN signals to a high-impedance state. When this bit is set to logic: • Zero, the Twisted Pair Interface is operational. ...
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... ICS1893CK-40 Pin Diagram P4RD TP_AP TP_AN VDD TP_BN TP_BP VSS AVDD 10TCSR 100TCSR 8.2 ICS1893CK-40 Pin Descriptions Table 8-1. ICS1893CK-40 MAC Interface Pins Signal Name MDIO MDC RXD3 RXD2 RXD1 ICS1893CK-40, Rev. C, 06/02/09 Chapter 8 Pin Diagram, Listings, and Descriptions 1 11 40-pin MLF Pin No. ...
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... ICS1893CK-40 Data Sheet Rev Release Table 8-1. ICS1893CK-40 MAC Interface Pins Signal Name RXD0 RXDV RXCLK RXER TXCLK TXEN TXD0 TXD1 TXD2 TXD3 Table 8-2. ICS 1893CF Multifunction Pins: PHY Address and LED Pins Signal Name P4RD P3TD P2LI P1CL P0AC Table 8-3. ICS1893CK-40 Configuration Pins ...
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... Transformer Interface Pins Transformer connections on the ICS1893CK-40 signals TP_AP, TP_AN, TP_BP and TP_BN are shown in Table 8.4. The previous TP_CT pin on the ICS1893AF is not used with the ICS1893CK-40. The typical Twisted Pair Transformers connections are shown in Chapter 5. The transformer must be 1:1 ratio and symetrical for 10/100 MDI/MDIX applications since the transmit twisted pair and receive twisted pair are interchangeable ...
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... This multi-function configuration pin is: – An input pin during either a power-on reset or a hardware reset. In this case, this pin configures the ICS1893CK-40 PHY Address Bit 1. – An output pin following reset. In this case, this pin provides collision status for the ICS1893CK-40 input pin: • ...
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... When the signal on this pin is: – De-asserted, this state indicates the ICS1893CK-40 does not have a link. – Asserted, this state indicates the ICS1893CK-40 has a valid link. Caution: This pin must not float. (See the notes at “Multi-Function (Multiplexed) Pins: PHY Address and LED Pins” ...
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... Low, that address bit is set to logic zero. – High, that address bit is set to logic one output pin: • When the signal on this pin is: – De-asserted, this state indicates the ICS1893CK-40 does not have Receive activity. – Asserted, this state indicates the ICS1893CK-40 has Receive activity. Caution: This pin must not float. (See the notes at “ ...
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... This pin is used with a crystal. Input (System) Reset (Active Low). • When the signal on this active-low pin is logic: – Low, the ICS1893CK- hardware reset. – High, the ICS1893CK-40 is operational. • For more information on hardware resets, see the following: – Section 4.1.2.1, “Hardware Reset” ...
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... The ICS1893CK-40, to transfer status information. All transfers and sampling are synchronous with the signal on the MDC pin. Note: If the ICS1893CK- used in an application that uses the mechanical MII specification, MDIO must have a 1.5 kΩ ±5% pull-up resistor at the ICS1893CK-40 end and a 2 kΩ ±5% pull-down resistor at the station management end ...
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... RXD0–RXD3 pins to the MAC Interface synchronously on the rising edges of RXCLK. Receive Data Valid. The ICS1893CK-40 asserts RXDV to indicate to the MAC that data is available on the MII Receive Bus (RXD[3:0]). The ICS1893CK-40: • Asserts RXDV after it detects and recovers the Start-of-Stream delimiter, /J/K/. (For the timing reference, see “ ...
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... Errors are detected during the reception of valid frames – A False Carrier is detected Note ICS1893CK-40 asserts a signal on the RXER pin upon detection of a False Carrier so that repeater applications can prevent the propagation of a False Carrier. 2. The RXER signal always transitions synchronously with RXCLK. ...
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... ICS1893CK-40 Data Sheet - Release 8.2.5 Ground and Power Pins Table 8-8. Ground and Power Pins Signal Name VDD VDD VDD VDD VDD AVDD VDDIO VSS VSS AVSS VSSIO ICS1893CK-40, Rev. C, 06/02/09 Chapter 8 Pin Diagram, Listings, and Descriptions Pin No. Signal Description Power 4 3.3V 12 3.3V 14 3.3V 35 3.3V 40 3.3V 8 3.3V Analog 32 3 ...
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... Stresses above these ratings can permanently damage the ICS1893CK-40. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the ICS1893CK-40 at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability ...
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... ICS1893CK-40 Data Sheet - Release 9.3 Recommended Component Values * Table 9-3. Recommended Component Values for ICS1893CK-40 Parameter Oscillator Frequency 10TCSR Resistor Value 100TCSR Resistor Value LED Resistor Value † There are two IEEE Std. 802.3 requirements that define the tolerance for the frequency of the oscillator. ...
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... Power-Down Supply Current† Reset † These supply current parameters are measured through VDD pins to the ICS1893CK-40. The supply current parameters include external transformer currents. ‡ Measurements taken with 100% data transmission and the minimum inter-packet gap. 9.4.2 DC Operating Characteristics for TTL Inputs and Outputs Table 9-5 lists the 3 ...
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... ICS1893CK-40 Data Sheet - Release 9.4.3 DC Operating Characteristics for REF_IN Table 9-6 lists the 3.3-V DC characteristics for the REF_IN pin. Note: The REF_IN input switch point is 50% of VDD. Table 9-6. 3.3-V DC Operating Characteristics for REF_IN Parameter Input High Voltage Input Low Voltage 9.4.4 DC Operating Characteristics for Media Independent Interface ...
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... ICS1893CK-40 Data Sheet Rev Release 9.5 Timing Diagrams 9.5.1 Timing for Clock Reference In (REF_IN) Pin Table 9-8 lists the significant time periods for signals on the clock reference in (REF_IN) pin. shows the timing diagram for the time periods. Note: The REF_IN switching point is 50% of VDD. ...
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... ICS1893CK-40 Data Sheet - Release 9.5.2 Timing for Transmit Clock (TXCLK) Pins Table 9-9 lists the significant time periods for signals on the Transmit Clock (TXCLK) pins for the various interfaces. Figure 9-3 shows the timing diagram for the time periods. Table 9-9. Transmit Clock Timing Time ...
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... ICS1893CK-40 Data Sheet Rev Release 9.5.3 Timing for Receive Clock (RXCLK) Pins Table 9-10 lists the significant time periods for signals on the Receive Clock (RXCLK) pins for the various interfaces. Figure 9-4 shows the timing diagram for the time periods. Table 9-10. MII Receive Clock Timing ...
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... ICS1893CK-40 Data Sheet - Release 9.5.4 100M MII: Synchronous Transmit Timing Table 9-11 lists the significant time periods for the 100M MII Interface synchronous transmit timing. The time periods consist of timings of signals on the following pins: • TXCLK • TXD[3:0] • TXEN • TXER Figure 9-5 shows the timing diagram for the time periods ...
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... ICS1893CK-40 Data Sheet Rev Release 9.5.5 10M MII: Synchronous Transmit Timing Table 9-12 lists the significant time periods for the 10M MII synchronous transmit timing. The time periods consist of timings of signals on the following pins: • TXCLK • TXD[3:0] • TXEN • TXER Figure 9-6 shows the timing diagram for the time periods ...
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... ICS1893CK-40 Data Sheet - Release 9.5.6 100M/MII Media Independent Interface: Synchronous Receive Timing Table 9-13 lists the significant time periods for the MII / 100M Stream Interface synchronous receive timing. The time periods consist of timings of signals on the following pins: • RXCLK • RXD[3:0] • RXDV • ...
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... MDC Period t4 MDC Rise Time to MDIO Valid t5 MDIO Setup Time to MDC t6 MDIO Hold Time after MDC † The ICS1893CK-40 is tested at 25 MHz (a 40-ns period) with a 50-pF load. Designs must account for all board loading of MDC. Figure 9-8. MII Management Interface Timing Diagram MDC t1 MDIO (Output) ...
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... ICS1893CK-40 Data Sheet - Release 9.5.8 10M Media Independent Interface: Receive Latency Table 9-15 lists the significant time periods for the 10M MII timing. The time periods consist of timings of signals on the following pins: • TP_RX (that is, the MII TP_RXP and TP_RXN pins) • RXCLK • ...
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... ICS1893CK-40 Data Sheet Rev Release 9.5.9 10M Media Independent Interface: Transmit Latency Table 9-16 lists the significant time periods for the 10M MII transmit latency. The time periods consist of timings of signals on the following pins: • TXEN • TXCLK • TXD (that is, TXD[3:0]) • ...
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... ICS1893CK-40 Data Sheet - Release 9.5.10 100M / MII Media Independent Interface: Transmit Latency Table 9-17 lists the significant time periods for the MII / 100 Stream Interface transmit latency. The time periods consist of timings of signals on the following pins: • TXEN • TXCLK • TXD (that is, TXD[3:0]) • ...
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... ICS1893CK-40 Data Sheet Rev Release 9.5.11 100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) Table 9-18 lists the significant time periods for the 100M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the following pins: • TXEN • TXCLK • ...
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... ICS1893CK-40 Data Sheet - Release 9.5.12 10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) Table 9-19 lists the significant time periods for the 10M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the following pins: • TXEN • TXCLK • ...
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... ICS1893CK-40 Data Sheet Rev Release 9.5.13 100M MII Media Independent Interface: Receive Latency Table 9-20 lists the significant time periods for the 100M MII / 100M Stream Interface receive latency. The time periods consist of timings of signals on the following pins: • TP_RX (that is, TP_RXP and TP_RXN) • ...
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... ICS1893CK-40 Data Sheet - Release 9.5.14 100M Media Independent Interface: Input-to-Carrier Assertion/De-Assertion Table 9-21 lists the significant time periods for the 100M MDI input-to-carrier assertion/de-assertion. The time periods consist of timings of signals on the following pins: • TP_RX (that is, TP_RXP and TP_RXN) • ...
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... ICS1893CK-40 Data Sheet Rev Release 9.5.15 Reset: Power-On Reset Table 9-22 lists the significant time periods for the power-on reset. The time periods consist of timings of signals on the following pins: • VDD • TXCLK Figure 9-16 shows the timing diagram for the time periods. Table 9-22. Power-On Reset Timing ...
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... ICS1893CK-40 Data Sheet - Release 9.5.16 Reset: Hardware Reset and Power-Down Table 9-23 lists the significant time periods for the hardware reset and power-down reset. The time periods consist of timings of signals on the following pins: • REF_IN • RESETn • TXCLK Figure 9-17 shows the timing diagram for the time periods. ...
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... ICS1893CK-40 Data Sheet Rev Release 9.5.17 10Base-T: Heartbeat Timing (SQE) Table 9-24 lists the significant time periods for the 10Base-T heartbeat (that is, the Signal Quality Error). The time periods consist of timings of signals on the following pins: • TXEN • TXCLK • COL Figure 9-18 shows the timing diagram for the time periods. ...
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... ICS1893CK-40 Data Sheet - Release 9.5.18 10Base-T: Jabber Timing Table 9-25 lists the significant time periods for the 10Base-T jabber. The time periods consist of timings of signals on the following pins: • TXEN • TP_TX (that is, TP_TXP and TP_TXN) • COL Figure 9-19 shows the timing diagram for the time periods. ...
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... ICS1893CK-40 Data Sheet Rev Release 9.5.19 10Base-T: Normal Link Pulse Timing Table 9-26 lists the significant time periods for the 10Base-T Normal Link Pulse (which consists of timings of signals on the TP_TXP pins). Table 9-26. 10Base-T Normal Link Pulse Timing Time Period t1 Normal Link Pulse Width ...
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... ICS1893CK-40 Data Sheet - Release 9.5.20 Auto-Negotiation Fast Link Pulse Timing Table 9-27 lists the significant time periods for the ICS1893CK-40 Auto-Negotiation Fast Link Pulse. The time periods consist of timings of signals on the following pins: • TP_TXP • TP_TXN Figure 9-21 shows the timing diagram for one pair of these differential signals, for example TP_TXP minus TP_TXN ...
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... ICS1893CK-40 Data Sheet Rev Release Chapter 10 Package Outline and Package Dimensions (40-pin, 6mm x 6mm MLF ) Package dimensions are kept current with JEDEC Publication No. 95 Seating Plane Index Area Top View D Millimeters Symbol Min Max A 0.80 1. 0.05 A3 0.25 Reference b 0.18 0.30 e 0.50 BASIC ...
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... ICS1893CK-40 Data Sheet - Release Chapter 11 Ordering Information Figure 11-1. shows ordering information for the ICS1893CK-40. Part / Order Number 1893CKI-40LF 1893CKI40LF 40-Lead MLF Lead/Pb-Free 1893CKI-40LFT 1893CKI40LF 40-Lead MLF Lead/Pb-Free, Tape and Reel ICS1893CK-40, Rev. C, 06/02/09 Marking Package Copyright © 2009, Integrated Device Technology, Inc. ...
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... ICS1893CK-40 Data Sheet Rev Release Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. www.idt.com ICS1893CK-40, Rev. C, 06/02/09 For Tech Support 408-284-4522 www.idt.com/go/clockhelp Copyright © 2009, Integrated Device Technology, Inc. ...