w83194br-655 Winbond Electronics Corp America, w83194br-655 Datasheet - Page 20

• Manufacturer Part Number: w83194br-655
• Description: Clock For Sis Chipsets Winbond Clock Generator
• Manufacturer: Winbond Electronics Corp America

7.20 Register 19: Slew rate Control (Default: D2h)
7.21 Register 20: Watch dog timer (Default: 88h)
7.22 Register 21: Fix Control (Default: 00h)
BIT
BIT
BIT
7
6
5
4
3
2
1
0
7
6
5
7
6
5
4
3
2
1
0
CPU1S_EN
CPU0S_EN
ZCLK_S2
ZCLK_S1
INV_USB48
USB48_S2
USB48_S1
MODE
Reserved
TRI-EN
FIX_ZCLK
FIX_PCI
SEC<6>
SEC<5>
SEC<4>
SEC<3>
SEC<2>
SEC<1>
SEC<0>
NAME
NAME
NAME
PWD
PWD
PWD
X
1
0
0
0
1
0
0
0
0
1
0
0
1
1
1
0
0
0
Stop CPU1 clocks, 1: Enable stop feature, 0: Disable
Stop CPU0 clocks, 1: Enable stop feature, 0: Disable
ZCLK1, 0 slew rate control
11: Strong, 00: Weak, 10/01: Normal
Invert the USB48 phase, 0: In phase with USB24_48
1: 180 degrees out of phase
USB48/USB12_48/USB24_48 slew rate control
11: Strong, 00: Weak, 10/01: Normal
Desktop / Mobile Mode (pin 4,pin16) selection, 1: Mobile mode
(CPUSTOP#, PCISTOP), 0: Desktop mode (Default)(RESET#,PCI0),
Default value follow hardware trapping data on MODE pin.
Reserved for test use, don’t modify it.
Setting the down count depth. One bit resolution Represent 250ms.
Default time depth is 8*250ms = 2.0 second. If the watchdog timer is
counting, this register will return present down count value.
Tri-state all output if set 1
ZCLK output frequency select mode
(Only valid under FIX_ADDR<2:0> is nonzero)
0: Output frequency according to frequency selection table
1: Output frequency according to FIX frequency table
PCI output frequency select mode
(Only valid under FIX_ADDR<2:0> is nonzero)
0: Output frequency according to frequency selection table
1: Output frequency according to FIX frequency table
W83194BR-655/W83194BG-655
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DESCRIPTION
DESCRIPTION
DESCRIPTION