cy7b9532v Cypress Semiconductor Corporation., cy7b9532v Datasheet - Page 4

• Manufacturer Part Number: cy7b9532v
• Description: Sonet Oc-48 Transceiver
• Manufacturer: Cypress Semiconductor Corporation.

Pin Descriptions
CY7B9532V OC-48 SONET Transceiver
Transmit Path Signals
TXDA[15:0]
TXCLKI
TXCLKO
Receive Path Signals
RXD[15:0]
RXCLK
Device Control and Status Signals
REFCLK±
LFI
RESET
LOCKREF
SD
FIFO_ERR
FIFO_RST
PWRDN
Receive Path Signals
CM_SER
RXCN1
RXCN2
RXCP1
RXCP
V
Loop Control Signals
DIAGLOOP
LINELOOP
REF
Name
HSTL inputs,
sampled by
TXCLKI
HSTL Clock input
HSTL Clock output
HSTL output,
synchronous
HSTL Clock output
Differential LVPECL
input
LVTTL output
LVTTL input
LVTTL input
LVTTL input
LVTTL output
LVTTL input
LVTTL input
Analog
Analog
Analog
Analog
Analog
HSTL Analog
Reference
LVTTL input
LVTTL input
I/O Characteristics
PRELIMINARY
Parallel Transmit Data Inputs. A 16-bit word, sampled by TXCLKI . TXD[15] is the most
significant bit (the first bit transmitted).
Parallel Transmit Data Input Clock
Transmit Clock Output. Divide by 16 of the selected transmit bit-rate clock
Parallel Receive Data Output. These outputs change following RXCLKO .
RXD[15] is the most significant bit of the output word, and is received first on the serial
interface.
Receive Clock Output. Divide by 16 of the bit-rate clock extracted from the received
serial stream.
Reference Clock. This clock input is used as the timing reference for the transmit and
receive PLLs. A derivative of this input clock may also be used to clock the transmit
parallel interface.
Line Fault Indicator. When LOW, this signal indicates that the selected receive data
stream has been detected as invalid by either a LOW input on SD, or by the receive VCO
being operated outside its specified limits.
Reset for all logic functions except the transmit FIFO.
Receive PLL Lock to Reference. When LOW, the receive PLL locks to REFCLK instead
of the received serial data stream.
Signal Detect. When LOW, the receive PLL locks to REFCLK instead of the received
serial data stream.
Transmit FIFO Error. When HIGH the transmit FIFO has either under or overflowed. The
FIFO must be reset to clear the error indication.
Transmit FIFO Reset. When LOW, the in and out pointers of the transmit FIFO are set
to maximum separation.
Device Power Down. When LOW, the logic and drivers are all disabled and placed into
a standby condition where only minimal power is dissipated.
Common Mode Termination. Capacitor shunt to V
Receive Loop Filter Capacitor (Negative)
Receive Loop Filter Capacitor (Negative)
Receive Loop Filter Capacitor (Positive)
Receive Loop Filter Capacitor (Positive)
V
Diagnostic Loopback Control. When HIGH, transmit data is routed through the receive
clock and data recovery and presented at the RXD[15:0] outputs. When LOW, received
serial data is routed through the receive clock and data recovery and presented at the
RXD[15:0] outputs.
Line Loopback Control. When HIGH, received serial data is looped back from receive
to transmit after being reclocked by a recovered clock. When LINELOOP is LOW, the
data passed to the OUT± line driver is controlled by LOOPA.
When both LINELOOP and LOOPA are LOW, the data passed to the OUT± line driver
is generated in the transmit shifter.
DDQ
/2.
4
Signal Description
SS
for common mode noise.
CY7B9532V