cy7b9532v Cypress Semiconductor Corporation., cy7b9532v Datasheet - Page 5

• Manufacturer Part Number: cy7b9532v
• Description: Sonet Oc-48 Transceiver
• Manufacturer: Cypress Semiconductor Corporation.

Pin Descriptions
CY7B9532V OC-48 SONET Transceiver
CY7B9532 Operation
The CY7B9532 is a highly configurable device designed to
support reliable transfer of large quantities of data, using high-
speed serial links. It performs necessary clock and data recov-
ery, clock generation, serial-to-parallel conversion, and paral-
lel-to-serial conversion. CY7B9532 also provides various loop-
back functions.
CY7B9532 Transmit Data Path
Operating Modes
The transmit path of the CY7B9532 supports 16-bit-wide data
paths.
Phase-Align Buffer
Data from the input register is passed to a phase-align buffer
(FIFO). This buffer is used to absorb clock phase differences
between the transmit input clock and the internal character
clock.
Initialization of the phase-align buffer takes place when the
FIFO_RST input is asserted LOW. When FIFO_RST is re-
turned HIGH, the present input clock phase relative to TXCLKI
is set. Once set, the input clock is allowed to skew in time up
to half a character period in either direction relative to
REFCLK; i.e., ±180°. This time shift allows the delay path of
the character clock (relative to REFLCK) to change due to op-
erating voltage and temperature, while not effecting the design
operation. FIFO_RST is an asynchronous input. FIFO_ERR is
the transmit FIFO Error indicator. When HIGH, the transmit
FIFO has either under or overflowed. The FIFO can be exter-
nally reset to clear the error indication or if no action is taken
the internal clearing mechanism will clear the FIFO in 9 clock
cycles. When the FIFO is being reset, the output data is 1010.
LOOPA
LOOPTIME
Serial I/O
OUT±
IN±
Power
V
V
V
V
V
CCN
SSN
CCQ
SSQ
DDQ
Name
LVTTL input
LVTTL input
Differential CML
output
Differential CML
input
Power
Ground
I/O Characteristics
(continued)
PRELIMINARY
Analog Line Loopback. When LINELOOP is LOW and LOOPA is HIGH, received serial
data is looped back from receive input buffer to transmit output buffer, but is not routed
through the clock and data recovery PLL. When LOOPA is LOW, the data passed to the
OUT± line driver is controlled by LINELOOP.
Loop Time Mode. When HIGH, the extracted receive bit-clock replaces transmit bit-
clock. When LOW, the REFCLK input is multiplied by 16 to generate the transmit bit
clock.
Differential Serial Data Output. This differential CML output (+3.3V referenced) is capa-
ble of driving terminated 50
modules.
Differential Serial Data Input. This differential input accept the serial data stream for
deserialization and clock extraction.
+3.3V Supply (for digital and low-speed I/O functions)
Signal and Power Ground (for digital and low-speed I/O functions)
+3.3V Quiet Power (for analog functions)
Quiet Ground (for analog functions)
+1.5V Supply for HSTL Outputs
5
Transmit PLL Clock Multiplier
The Transmit PLL Clock Multiplier accepts a 155.52-MHz ex-
ternal clock at the REFCLK input, and multiplies that clock by
16 to generate a bit-rate clock for use by the transmit shifter.
The operating serial signaling rate and allowable range of
REFCLK frequencies is listed in Table 7. The REFCLK± input
is a standard PECL input.
Serializer
The parallel data from the phase-align buffer is passed to the
Serializer which converts the parallel data to serial data using
the bit-rate clock generated by the Transmit PLL clock multipli-
er. TXD[15] is the most significant bit of the output word, and
is transmitted first on the serial interface.
Serial Output Driver
The serial interface Output Driver makes use of high-perfor-
mance differential CML (Current Mode Logic) to provide a
source-matched driver for the transmission lines. This driver
receives its data from the Transmit Shifters or the receive loop-
back data. The outputs have signal swings equivalent to that
of standard PECL drivers, and are capable of driving AC-
coupled optical modules or transmission lines.
CY7B9532 Receive Data Path
Serial Line Receivers
A differential line receiver, IN is available for accepting the
input serial data stream. The serial line receiver inputs can
accommodate high wire interconnect and filtering losses or
transmission line attenuation (V
to-peak differential) and can be AC-coupled to +3.3V or +5V
powered fiber-optic interface modules. The common-mode tol-
transmission lines or commercial fiber-optic transmitter
Signal Description
DIF
> 125 mV, or 250 mV peak-
CY7B9532V