cy7b9532v Cypress Semiconductor Corporation., cy7b9532v Datasheet - Page 6

• Manufacturer Part Number: cy7b9532v
• Description: Sonet Oc-48 Transceiver
• Manufacturer: Cypress Semiconductor Corporation.

erance of these line receivers accommodates a wide range of
signal termination voltages.
Lock to Data Control
Line Receiver routed to the clock and data recovery PLL is
monitored for
This status is presented on the LFI (Link Fault Indicator) out-
put, which changes asynchronously in the cases when SD or
LOCKREF goes from HIGH to LOW. Otherwise, it changes
synchronous to the REFCLK.
Clock/Data Recovery
The extraction of a bit-rate clock and recovery of data bits from
received serial stream is performed by a Clock/Data Recovery
(CDR) block. The clock extraction function is performed by
high-performance embedded phase-locked loop (PLL) that
tracks the frequency of the incoming bit stream and aligns the
phase of the internal bit-rate clock to the transitions in the se-
lected serial data stream.
CDR accepts a character-rate (bit-rate
on the REFCLK input. This REFCLK input is used to ensure
that the VCO (within the CDR) is operating at the correct fre-
quency (rather than some harmonic of the bit-rate), to improve
PLL acquisition time, and to limit unlocked frequency excur-
sions of the CDR VCO when no data is present at the serial
inputs.
Regardless of the type of signal present, the CDR will attempt
to recover a data stream from it. If the frequency of the recov-
ered data stream is outside the limits set by the range controls,
the CDR PLL will track REFCLK instead of the data stream.
When the frequency of the selected data stream returns to a
valid frequency, the CDR PLL is allowed to track the received
data stream. The frequency of REFCLK is required to be within
±200 ppm of the frequency of the clock that drives the
REFCLK signal of the remote transmitter to ensure a lock to
the incoming data stream.
For systems using multiple or redundant connections, the LFI
output can be used to select an alternate data stream. When
an LFI indication is detected, external logic can toggle selec-
tion of the input device. When such a port switch takes place,
it is necessary for the PLL to re-acquire lock to the new serial
stream.
External Filter
The CDR circuit uses external capacitors for the PLL filter. A
0.1- F capacitor needs be connected between RXCN1 and
RXCP1. Similarly a 0.1- F capacitor needs to be connected
between RXCN2 and RXCP2. The recommended capacitors
for the external filters are 0805 NPO or 0603 NPO.
Deserializer
The CDR circuit extracts bits from the serial data stream and
clocks these bits into the Deserializer at the bit-clock rate. The
Deserializer converts serial data into parallel data. RXD[15] is
the most significant bit of the output word and is received first
on the serial interface.
• status of signal detect (SD) pin
• status of LOCKREF pin
• received data stream outside normal frequency range
(±200 ppm)
PRELIMINARY
16) reference clock
6
Loopback/Timing Modes
CY7B9532V supports various loopback modes as described
below.
Facility Loopback (line loopback with retiming)
When the LINELOOP signal is set HIGH, the Facility Loopback
mode is activated and the high-speed serial receive data (IN±)
is presented to the high-speed transmit output (OUT±) after
retiming. In Facility Loopback mode, the high-speed receive
data (IN±) is also converted to parallel data and presented to
the low-speed receive data output pins (RXD[15:0]). The re-
ceive recovered clock is also divided down and presented to
the low speed clock output (RXCLK).
Equipment Loopback (diagnostic loopback with retiming)
When the DIAGLOOP signal is set HIGH, transmit data is
looped back to the RX PLL, replacing IN±. Data is looped back
from the parallel TX inputs to the parallel RX outputs. The data
is looped back at the internal serial interface and goes through
transmit shifter and the receive CDR. SD is ignored in this
mode.
Line Loopback Mode (non-retimed data)
When the LOOPA signal is set HIGH, the RX serial data is
directly buffered out to the transmit serial data. The data at the
serial output is not retimed.
Loop Timing Mode
When the LOOPTIME signal is set HIGH, the TX PLL is by-
passed and receive bit-rate clock is used for transmit side
shifter.
Reset Modes
ALL logic circuits in the device can be reset using RESET and
FIFO_RST signals. When RESET is set LOW, all logic circuits
except FIFO are internally reset. When FIFO_RST is set LOW,
the FIFO logic is reset.
Power-down Mode
CY7B9532 provides a global power-down signal PWRDN.
When LOW, this signal powers down the entire device to a
minimal power dissipation state. RESET and FIFO_RST sig-
nals should be asserted LOW along with PWRDN signal to
ensure low power dissipation.
PECL Compliance
The CY7B9532V HSTL parallel I/O can be configured to
LVPECL compliance with slight termination modifications. On
the transmit side of the transceiver, the TXD[15:0] and TXCLK
can be made LVPECL compliant by setting V
voltage of a LVPECL signal) to V
LVPECL signal on the receiver side of the transceiver, the
transmission lines need to be terminated with the Thévenin
equivalent of Zo at LVPECL ref. Next the signal is attenuated
using a series resistor at the driver end of the line to reduce
the HSTL voltage swing level to an LVPECL swing level (see
Figure 6). This circuit needs to be used on all 16 RXD[15:0]
pins and the RXCLK. The voltage divider has been calculated
assuming the system is built with 50
CC
–1.33 volts. To emulate a
transmission lines.
CY7B9532V
REF
(reference