mc1451a-e ETC-unknow, mc1451a-e Datasheet - Page 13

• Manufacturer Part Number: mc1451a-e
• Description: Advanced Brushless Motor Control Chipset
• Manufacturer: ETC-unknow

Pin Descriptions
The following tables provide pin descriptions for the MC1231-series chipsets.
IC
I/O Chip Pinouts
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Pin Name
QuadA1
QuadB1
QuadA2
QuadB2
~Index1
~Index2
~Home1
~Home2
DACSlct
CPClk
I/OClkIn
I/OClkOut
CPAddr0
CPAddr1
CPAddr2
CPAddr3
~CPWrite
CPCntrl0
CPCntrl1
CPCntrl2
CPCntrl3
HostCmd
Pin #
28
42
26
30
24
9
13
23
33
46
52
45
68
27
29
12
2
20
36
22
63
41
Description/Functionality
Quadrature A, B channels for axis 1 - 2 (input). Each of these 2 pairs of quadrature (A, B)
signals provide the position feedback for an incremental encoder. When the encoder is
moving in the positive, or forward direction, the A signal leads the B signal by 90 degs.
NOTE: Many encoders require a pull-up resistor on each of these signals to establish a
proper high signal (check the encoder electrical specifications)
NOTE: For MC1231A all 4 pins are valid. For MC1131A pins for axes 1 only are valid. Invalid
axis pins can be left unconnected
Index encoder signals for axis 1-2 (input). Each of these 2 signals indicate the index flag
state from the encoder. A valid index pulse is recognized by the chip set when the index flag
transitions low, followed by the corresponding A and B channels of the encoder transitioning
low. The index pulse is recognized at the later of the A or B transitions. If not used this signal
must be tied high.
NOTE: For MC1231A both pins are valid. For MC1131A pins for axes 1 only are valid.
Invalid axis pins can be left unconnected.
Home signals for axis 1-2 (input). Each of these signals provide a general purpose input to
the hardware position capture mechanism. A valid home signal is recognized by the chipset
when the home flag transitions low. These signals have a similar function as the ~Index
signals, but are not gated by the A and B encoder channels. For valid axis pins, If not used,
this signal must be tied high. See below for valid pin definitions for the MC1231A and
MC1131A.
NOTE: For MC1231A both pins are valid. For MC1131A pins for axes 1 only are valid.
Invalid axis pins can be left unconnected.
DAC Select (output). This signal is asserted high to select any of the available DAC output
channels. For details on DAC decoding see description of DAC16Addr0-1 signals.
I/O chip clock (input). This signal is connected directly to the ClkOut pin (CP chip) and
provides the clock signal for the I/O chip. The frequency of this signal is 1/4 the user-provided
ClkIn (CP chip) frequency.
Phase shifted clock (input). This signal must be connected to I/OClkOut (I/O chip), and inputs
a phase shifted clock signal.
Phase shifted clock (output). This signal must be connected to I/OClkIn (I/O chip), and
outputs a phase shifted clock signal.
I/O chip to CP chip communication address (input). These 4 signals are connected to the
corresponding I/OAddr0-3 pins (CP chip), and together provide addressing signals to
facilitate CP to I/O chip communication.
I/O chip to CP chip communication write (input). This signal is connected to the ~I/OWrite pin
(CP chip) and provides a write strobe to facilitate CP to I/O chip communication.
I/O chip to CP chip communication control (mixed). These 4 signals are connected to the
corresponding I/OCntrl0-3 pins (CP chip), and provide control signals to facilitate CP to I/O
chip communication.
Host Port Command (input). This signal is asserted high to write a host command to the chip
set. It is asserted low to read or write a host data word to the chipset
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