mc1451a-e ETC-unknow, mc1451a-e Datasheet - Page 62

• Manufacturer Part Number: mc1451a-e
• Description: Advanced Brushless Motor Control Chipset
• Manufacturer: ETC-unknow

Application Notes
Interfacing MC1231A to ISA bus.
A complete, ready-to-use ISA (PC/AT) bus interface circuit has been
provided to illustrate MC1231A host interfacing, as well as to make it
easier for the customer to build an MC1231A-based system.
The interface between the PMD MC1231A chip set and the ISA (PC-
AT) Bus is shown on the following page.
Comments on Schematic
This interface uses a 22V10 PAL and a 74LS245 to buffer the data
lines.This interface assumes a base address is assigned in the address
space of A9-A0. 300-400 hex These addresses are generally available
for prototyping and other system-specific uses without interfering with
system assignments. This interface occupies 16 addresses from XX0 to
XXF hex though it does not use all the addresses. Two select lines are
provided allowing the base address to be set to 340,350,370 and 390
hex for the select lines S1,S0 equal to 0,1,2,and 3 respectively.The
address assignments used are as follows, where BADR is the base
address, 340 hex for example:
Address
340h
342h
344h
348h
The base address (BADR) is decoded in ADRDEC. It is nanded with
SA2:SA3, BADR+0, (B+0) to form -HSEL to select the I/O chip. B+0
nanded with IOR* forms -HRD, host read, directly. The 22V10 tail-bites
the write pulse since the setup time is greater than necessary on the
bus some of the bus duration is used to generate data hold time at the
I/O chip. -HWR, host write is set the first clock after B+0 and IOW* is
recognized. The next clock sets TOG and clears -HWR. TOG remains
set holding -HWR clear until IOW* is unasserted on the bus indicating
the end of the bus cycle. B+4 and IOR* out enables HRDY to SD7 so
the status of HRDY may be tested. SD7 is used since the sign bit of a
byte may be easily tested. The rest of the data bits are left floating and
should be ignored. B+8 and IOW* generate a reset pulse which will init
the interface by clearing the two write registers and outputs a reset
pulse, -RS, for the CP chip. The reset instruction is OR'd with RESET
on the bus to initialize the PMD chip set when the PC is reset.
use
read-write data
write command
read status (HostRdy) [D7 only]
write reset [Data= don't care]
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