mc145201 Freescale Semiconductor, Inc, mc145201 Datasheet - Page 10

• Manufacturer Part Number: mc145201
• Description: 2.0 Ghz Pll Frequency Synthesizer
• Manufacturer: Freescale Semiconductor, Inc

C register. If desired, PD out can be forced to a floating state
by utilization of the disable feature in the C register (bit C6).
This is a patented feature. Similarly, PD out is forced to the
floating state when the device is put into standby (STBY bit
C4 = high).
gain is controllable by bits C3, C2, and C1: gain (in amps per
radian) = PD out current divided by 2 .
Double–Ended Phase/Frequency Detector Outputs
loop error signal. Through use of a Motorola patented tech-
nique, the detector’s dead zone has been eliminated. There-
fore, the phase/frequency detector is characterized by a
linear transfer function. The operation of the phase/frequen-
cy detector is described below and is shown in Figure 18.
changed via C register bits C6 or C4. This is a patented fea-
ture. Note that when disabled or in standby, R and V are
forced to their rest condition (high state).
GND to V PD .
LD
Lock Detector Output (Pin 2)
going pulses when the loop is locked (f R and f V of the same
phase and frequency). The output pulses low when f V and f R
are out of phase or different frequencies. LD is the logical
ANDing of R and V (see Figure 18).
This is a patented feature. Upon power up, on–chip initializa-
tion circuitry disables LD to a static low logic level to prevent
a false “lock” signal. If unused, LD should be disabled and
left open.
V DD .
R and V (Pins 3 and 4)
MC145201
10
Frequency and Phase of f V = f R : essentially a floating
This output can be enabled, disabled, and inverted via the
The PD out circuit is powered by V PD . The phase detector
These outputs can be combined externally to generate a
POL bit (C7) in the C register = low (see Figure 15)
Frequency of f V > f R or Phase of f V Leading f R : V = nega-
Frequency of f V < f R or Phase of f V Lagging f R : V = essen-
Frequency and Phase of f V = f R : V and R remain essen-
POL bit (C7) = high
Frequency of f V > f R or Phase of f V Leading f R : R = nega-
Frequency of f V < f R or Phase of f V Lagging f R : R = essen-
Frequency and Phase of f V = f R : V and R remain essen-
These outputs can be enabled, disabled, and inter-
The R and V output signal swing is approximately from
This output is essentially at a high level with narrow low–
This output can be enabled and disabled via the C register.
The LD output signal swing is approximately from GND to
state; voltage at pin determined by loop filter
tive pulses, R = essentially high
tially high, R = negative pulses
tially high, except for a small minimum time period when
both pulse low in phase
tive pulses, V = essentially high
tially high, V = negative pulses
tially high, except for a small minimum time period when
both pulse low in phase
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005
Rx
External Resistor (Pin 8)
with bits in the C register, determines the amount of current
that the PD out pin sinks and sources. When bits C2 and C3
are both set high, the maximum current is obtained at PD out ;
see Tables 2 and 3 for other values of current. To achieve a
maximum current of 2 mA, the resistor should be about
18 k
current values are desired.
floated.
TEST POINT PINS
TEST 1
Modulus Control Signal (Pin 9)
access to the on–board 64/65 prescaler. When Test 1 is low,
the prescaler divides by 65. When high, the prescaler divides
by 64.
TEST 2
Prescaler Output (Pin 13)
prescaler output.
POWER SUPPLY PINS
V DD
Positive Power Supply (Pin 14)
of the device. The voltage range is + 4.5 to + 5.5 V with re-
spect to the GND pin.
GND using a low–inductance capacitor mounted very close
to these pins. Lead lengths on the capacitor should be
minimized.
V CC
Positive Power Supply (Pin 12)
scaler. The voltage range is + 4.5 to + 5.5 V with respect to
the GND pin. In the standby mode, the V CC pin still draws a
few milliamps from the power supply. This current drain can
be eliminated with the use of transistor Q1 as shown in
Figure 22.
GND using a low–inductance capacitor mounted very close
to these pins. Lead lengths on the capacitor should be
minimized.
A resistor tied between this pin and GND, in conjunction
When the R and V outputs are used, the Rx pin may be
This pin may be used in conjunction with the Test 2 pin for
This pin may be used to access to the on–board 64/65
This pin supplies power to the main CMOS digital portion
For optimum performance, V DD should be bypassed to
This pin supplies power to the RF amp and 64/65 pre-
For optimum performance, V CC should be bypassed to
This pin is an unbuffered output and must be
floated in an actual application. This pin must be
attached to an isolated pad with no trace.
This pin is an unbuffered output and must be
floated in an actual application. This pin must be
attached to an isolated pad with no trace.
when V PD is 5.0 V. See Figure 14 if lower maximum
MOTOROLA WIRELESS SEMICONDUCTOR
CAUTION
CAUTION
SOLUTIONS DEVICE DATA