hsp43168 Intersil Corporation, hsp43168 Datasheet - Page 4

• Manufacturer Part Number: hsp43168
• Description: Dual Fir Filter
• Manufacturer: Intersil Corporation

Pin Description
SYMBOL
CSEL0-4
OUT9-27
SHFTEN
MUX0-1
ACCEN
CIN0-9
INA0-9
INB0-9
FWRD
RVRS
TXFR
GND
A0-8
OEH
V
CLK
OEL
WR
CC
TYPE
I/O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
V
Ground.
Control/Coefficient Data Bus. Processor interface for loading control data and coefficients. CIN0 is the LSB.
Control/Coefficient Address Bus. Processor interface for addressing Control and Coefficient Registers. A0 is the
LSB.
Control/Coefficient Write Clock. Data is latched into the Control and Coefficient Registers on the rising edge of
WR.
Coefficient Select. This input determines which of the 32 coefficient sets are to be used by FIR A and B. This input
is registered and CSEL0 is the LSB.
Input to FIR A. INA0 is the LSB.
Bidirectional Input for FIR B. INB0 is the LSB and is input only. When used as output, INB1-9 are the LSBs of the
output bus, and INB9 is the MSB of these bits.
19 MSBs of Output Bus. Data format is either unsigned or two's complement depending on configuration. OUT27
is the MSB.
Shift Enable. This active low input enables clocking of data into the part and shifting of data through the Decimation
Registers.
Forward ALU Input Enable. When active low, data from the forward decimation path is input to the ALUs through
the “a” input. When high, the “a” inputs to the ALUs are zeroed.
Reverse ALU Input Enable. When active low, data from the reverse decimation path is input to the ALUs through
the “b” input. When high, the “b” inputs to the ALUs are zeroed.
Data Transfer Control. This active low input switches the LIFO being read into the reverse decimation path with
the LIFO being written from the forward decimation path (see Figure 1).
Adder/Mux Control. This input controls data flow through the output Adder/Mux. Table 5 lists the various
configurations.
Clock. All inputs except those associated with the processor interface (CIN0-9, A0-8, WR) and the output enables
(OEL, OEH) are registered by the rising edge of CLK.
Output Enable Low. This three-state control enables the LSBs of the output bus to INB1-9 when OEL is low.
Output Enable High. This three-state control enables OUT9-27 when OEH is low.
Accumulate Enable. This active high input allows accumulation in the FIR Cell Accumulator. A low on this input
latches the FIR Accumulator contents into the Output Holding Registers while zeroing the feedback pass in the
Accumulator.
4
CC
: +5V power supply pin.
HSP43168
DESCRIPTION