hsp43168 Intersil Corporation, hsp43168 Datasheet - Page 9

• Manufacturer Part Number: hsp43168
• Description: Dual Fir Filter
• Manufacturer: Intersil Corporation

Coefficient sets may be switched every clock to support
polyphase filtering operations.
The coefficients are loaded into On-Board Registers using
the microprocessor interface, CIN0-9, A0-8, and WR. Each
multiplier within the FIR Cells is driven by a coefficient bank
with one of 32 coefficients. These coefficients are addressed
as shown in Table 4. The inputs A0-1 specify the Coefficient
Bank for one of the four multipliers in each FIR Cell; A2
specifies FIR Cell A or B; Bits A7-3 specify one of 32 sets in
which the coefficient is to be stored. For example, an
address of 10dH would access the coefficient for the second
multiplier in FIR B in the second coefficient set.
FIR Cell Accumulator
The registered outputs from the multipliers in each FIR cell
feed an accumulator. The ACCEN input controls each
accumulator's running sum and the latching of data from the
accumulator into the Output Holding Registers. When
ACCEN is low, feedback from the accumulator adder is
zeroed which disables accumulation. Also, output from the
accumulator is latched into the Output Holding Registers.
When ACCEN is asserted, accumulation is enabled and the
contents of the Output Holding Registers remain unchanged.
COEFF
FIR
A8
1
1
1
1
1
1
1
1
.
TABLE 4. FIR COEFFICIENT WRITE ADDRESSES
CSEL (4-0)
COEFF.
xxxx x
xxxx x
xxxx x
xxxx x
xxxx x
xxxx x
xxxx x
xxxx x
A7-3
SET
CELL
A/B
A2
0
0
0
0
1
1
1
1
MULTIPLIER
9
A1-0
00
01
10
11
00
01
10
11
DESTINATION
FIR
A
A
A
A
B
B
B
B
BANK
0
1
2
3
0
1
2
3
HSP43168
Output MUX/Adder
The contents of each FIR Cell's Output Holding Register is
summed or multiplexed in the Mux/Adder. The operation of
the Mux/Adder is controlled by the MUX1-0 inputs as
shown in Table 5. Applications requiring 10-bit data and 20-
bit coefficients or 20-bit data and 10-bit coefficients are
made possible by configuring the MUX/Adder to scale FIR
B's output by 2
Dual FIR is configured as two independent filters, the
MUX1-0 inputs would be used to multiplex the filter outputs
of each cell. For applications in which FIR A and B are
configured as a single filter, the MUX/Adder is configured to
sum the output of each FIR cell.
NOTE: While a 20-bit coefficient filter is a single filter, the mode
select is set to 1 and MUX1-0 is set to 00.
MUX1-0
00
01
10
11
TABLE 5. MUX1-0 BIT DEFINITIONS
-10
prior to summing with FIR A. When the
FIRA + FIRB (FIR B Scaled by 2
FIRA + FIRB
FIRA
FIRB
MUX1-0 DECODING
OUT0-27
-10
)