hsp48410 Intersil Corporation, hsp48410 Datasheet - Page 11

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hsp48410

Manufacturer Part Number
hsp48410
Description
Histogrammer/accumulating Buffer
Manufacturer
Intersil Corporation
Datasheet

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AC Electrical Specifications
NOTES:
Test Load Circuit
FCT0-2 Hold from LD
START Setup to CLK
START Hold from CLK
PIN0-9 Setup Time
PIN0-9 Hold Time
LD Pulse Width
LD Setup to START
WR Low
WR High
Address Setup
Address Hold
DIO Setup to WR
DIO Hold from WR
RD Low
RD High
RD Low to DIO Valid
Read/Write Cycle Time
DIO Valid after RD High
Output Enable Time
Output Disable Time
Output Rise Time
Output Fall Time
6. AC Testing is performed as follows: Input levels (CLK) 0.0V and 4.0V; input levels (all other inputs) 0V and 3.0V. Timing reference levels (CLK)
7. There must be at least one rising edge of CLK between the rising edge of LD and the falling edge of START.
8. Characterized upon initial design and after major changes to design and/or process.
9. Transition is measured at 200mV from steady state voltage with loading as specified in test load circuit with C
= 2.0V, (all others) = 1.5V. Output load circuit with C
INCLUDES STRAY AND JIG CAPACITANCE
PARAMETER
SWITCH S1 OPEN FOR I
11
V
CC
SYMBOL
= 5V
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WH
WS
WH
SH
PH
WL
AH
RH
RD
CY
OH
OE
OD
FH
SS
PS
LS
AS
RL
t
t
LL
R
F
DUT
CCSB
5%, T
L
C
Note 7
Note 8
Note 9
Note 8
From 0.8V to 2.0V, Note 8
From 2.0V to 0.8V, Note 8
AND I
= 40pF. Output transition measured at V
A
L
= 0
CCOP
o
HSP48410
C to 70
S
1
o
NOTES
C (Note 6) (Continued)
EQUIVALENT CIRCUIT
IOH
1.5V
-40 (40 MHz)
MIN
T
OH
12
12
10
12
12
13
12
35
15
55
CP
0
0
0
1
1
-
-
-
-
-
-
IOL
1.5V and V
MAX
35
18
18
0
6
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
L
OL
-33 (33 MHz)
MIN
T
= 40pF.
13
13
12
15
15
15
15
43
17
65
CP
0
0
0
1
1
-
-
-
-
-
-
1.5V.
MAX
43
19
19
0
6
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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