hsp48410 Intersil Corporation, hsp48410 Datasheet - Page 7

• Manufacturer Part Number: hsp48410
• Description: Histogrammer/accumulating Buffer
• Manufacturer: Intersil Corporation

Histogram Accumulate Mode
This function is very similar to the Histogram function. In this
case, a counter is used to provide the address data to the
RAM. The RAM is sequentially accessed, and the data from
each bin is added to the data from the previous bins. This
accumulation of data continues until the function is halted.
The results of the accumulation are displayed on the DIO
bus while simultaneously being written back to the RAM.
When the operation is complete, the RAM will contain the
Cumulative Distribution Function (CDF) of the image.
Figure 4 shows the configuration for this mode. Once this
function is selected, the START pin is used to reset the
counter and enable writing to the RAM. Write enable is
delayed 3 cycles to match the delay in the Address
Generator. The START pin determines when the
accumulation will begin. Before this pin is activated, the
counter will be in an unknown state and the DIO bus will
contain unpredictable data. Once the START pin is sampled
low, the data registers are reset in order to clear the
accumulation. The output (DIO bus) will then be zero until a
nonzero data value is read from the RAM. Timing for this
operation is shown in Figure 5.
The START pin must remain low in order to allow the
accumulated data to overwrite the original histogram data
contained in the RAM. When the START pin returns to a high
state, the configuration remains intact, but writing to the
START
(RD LOW)
CLK
DIO 0-23
FIGURE 4. HISTOGRAM ACCUMULATE MODE BLOCK
START
FIGURE 5. HISTOGRAM ACCUMULATE MODE TIMING
CLK
CONTROL
DIAGRAM
GENERATOR
IN
ADDRESS
COUNTER
ADDRESS
RAM
OUT
7
S
OUT 0 OUT 1 OUT 2
DIO
RD
I/F
0-23
DIO
HSP48410
RAM is disabled and the part is in LUT(read) mode. Note
that the counter is not reset at this point. The counter will be
reset on the first cycle of CLK that START is detected low. To
prevent invalid data from being written to the RAM, when the
counter reaches its maximum value (1023), further writing to
the RAM is disabled and the counter remains at this value
until the mode is changed.
At the end of the histogram accumulation, the DIO output
bus will contain the last accumulated value. The chip will
remain in this state until START becomes inactive. The
results of the accumulation can then be read out
synchronously by keeping START high, or asynchronously in
either of the asynchronous modes.
Bin Accumulate Mode
The functionality of this mode is also similar to the Histogram
function. The only difference is that instead of incrementing
the bin data by 1, the bin data is added to the incoming DIN
bus data. The DIN bus is delayed internally by 3 cycles to
match the latency in the address generator. Figure 6 shows
the block diagram of the internal configuration for this mode,
while the timing is given in Figure 7. Note that in this figure,
START is used to disregard the data on DIN0-23 during
DATA2.
(RD LOW)
DIN 0-23
DIO 0-23
DIN 0-23
PIN 0-9
START
PIN 0-9
START
CLK
FIGURE 6. BIN ACCUMULATE BLOCK DIAGRAM
CONTROL
FIGURE 7. BIN ACCUMULATE TIMING
ADDRESS
DATA
ADD. 0
DATA 0
GENERATOR
IN
ADDRESS
ADDRESS
RAM
ADD. 1
DATA 1
OUT
ADD. 2
“0”
DATA 2 DATA 3
ORIGINAL BIN CONTENTS
ADD. 3
ARE NOT UPDATED
OUTPUT
OUT 0
ADD. 4
DATA 4
OUT 1
ADD. 5
DATA 5
RD
DIO
I/F
DIO 0-23
OUT 2