pcf8563 NXP Semiconductors, pcf8563 Datasheet - Page 13

• Manufacturer Part Number: pcf8563
• Description: Real-time Clock/calendar
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCF8563_5
Product data sheet
Fig 11. System configuration
SCL
SDA
TRANSMITTER /
8.1 Bit transfer
8.2 Start and stop conditions
8.3 System configuration
RECEIVER
MASTER
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P); see
A device generating a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message is the master and the devices which are
controlled by the master are the slaves (see
Fig 9. Bit transfer
Fig 10. Definition of start and stop conditions
SDA
SCL
RECEIVER
START condition
SLAVE
SDA
SCL
Figure
S
Rev. 05 — 17 July 2007
10.
TRANSMITTER /
RECEIVER
SLAVE
data valid
data line
stable;
Figure
Figure
allowed
change
of data
TRANSMITTER
9).
MASTER
11).
STOP condition
Real time clock/calendar
TRANSMITTER /
mbc621
RECEIVER
P
MASTER
PCF8563
© NXP B.V. 2007. All rights reserved.
mba605
mbc622
SDA
SCL
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