pcf8532 NXP Semiconductors, pcf8532 Datasheet - Page 13

• Manufacturer Part Number: pcf8532
• Description: Universal Lcd Driver For Low Multiplex Rates
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCF8532_1
Product data sheet
7.5.1 Internal clock
7.5.2 External clock
7.5 Oscillator
7.6 Timing and frame frequency
7.7 Display register
7.8 Segment outputs
The internal logic and the LCD drive signals of the PCF8532 are timed by a frequency f
which either is derived from the built-in oscillator frequency f
external clock frequency f
The clock frequency f
The internal logic and the LCD drive signals of the PCF8532 are timed either by the
built-in oscillator or by an external clock.
The internal oscillator is enabled by connecting pin OSC to pin V
from pin CLK provides the clock signal for cascaded PCF8532’s in the system. However,
the clock signal is only available at the pin CLK, if the display is enabled. The display is
enabled using the display enable bit (see
The nominal output clock frequency is like specified in
Connecting pin OSC to V
external clock input.
A clock signal must always be supplied to the device; removing the clock may freeze the
LCD in a DC state.
The timing of the PCF8532 organizes the internal data flow of the device. This includes
the transfer of display data from the display RAM to the display segment outputs.
In cascaded applications, the synchronization signal (SYNC) maintains the correct timing
relationship between all the PCF8532’s in the system.
The clock frequency can be programmed by software such that the nominal frame
frequency can be chosen in steps of 5 Hz in the range of 60 Hz to 90 Hz (see
The display register holds the display data while the corresponding multiplex signals are
generated. There is a one-to-one relationship between the data in the display register, the
LCD segment outputs and one column of the display RAM.
The LCD drive section includes 160 segment outputs (S0 to S159) which must be
connected directly to the LCD. The segment output signals are generated in accordance
with the multiplexed backplane signals and with data residing in the display register. When
less than 160 segment outputs are required the unused segment outputs must be left
open-circuit.
clk
Rev. 1 — 10 February 2009
determines the LCD frame frequency f
DD
clk(ext)
enables an external clock source. Pin CLK then becomes the
(
f
clk
=
f
clk ext
Table
Universal LCD driver for low multiplex rates
).
9).
Table 18
osc
fr
(
with parameter f
SS
f
(see
clk
. In this case the output
=
Table
PCF8532
--------- -
© NXP B.V. 2009. All rights reserved.
f
64
osc
) or equals an
15).
Table
clk
.
13 of 44
15).
clk