pcf8532 NXP Semiconductors, pcf8532 Datasheet - Page 20

• Manufacturer Part Number: pcf8532
• Description: Universal Lcd Driver For Low Multiplex Rates
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCF8532_1
Product data sheet
7.16.4 Acknowledge
7.16.5 I
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during
which time the master generates an extra acknowledge related clock pulse.
Acknowledgement on the I
The PCF8532 acts as an I
transmit data to an I
the acknowledge signals of the selected devices. Device selection depends on the
I
subaddress.
In single device application, the hardware subaddress inputs A0 and A1 are normally tied
to V
and A1 are tied to V
two devices with a common I
2
2
Fig 14. Acknowledgement on the I
•
•
•
•
C-bus slave address, on the transferred command data and on the hardware
C-bus controller
SS
A slave receiver which is addressed must generate an acknowledge after the
reception of each byte.
Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
which defines the hardware subaddress 0. In multiple device applications A0
by transmitter
data output
by receiver
data output
SCL from
master
2
SS
condition
START
C-bus master receiver. The only data output from the PCF8532 are
Rev. 1 — 10 February 2009
or V
S
2
2
DD
C-bus slave receiver. It does not initiate I
C-bus is shown in
2
C-bus slave address have the same hardware subaddress.
in accordance with a binary coding scheme such that no
1
2
C-bus
Universal LCD driver for low multiplex rates
Figure
2
14.
not acknowledge
acknowledge
8
2
acknowledgement
C-bus transfers or
clock pulse for
PCF8532
© NXP B.V. 2009. All rights reserved.
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