m48t212a STMicroelectronics, m48t212a Datasheet - Page 14

• Manufacturer Part Number: m48t212a
• Description: 3.3v Timekeeper Controller
• Manufacturer: STMicroelectronics

M48T212A
V
Vccsw output goes low when V
V
MOSFET
MTD20P06HDL is recommended. This MOSFET
in turn connects V
the current requirement is greater than I
Table 7). This output may also be used simply to
indicate the status of the internal battery switcho-
ver comparator, which controls the source (V
battery) of the V
POWER-ON RESET
The M48T212A continuously monitors V
V
pulls low (open drain) and remains low on power-
up for 40 to 200ms after V
RST pin is an open drain output and an appropri-
ate pull-up resistor to V
control rise time.
Note: If the RST output is fed back into either of
the RSTIN inputs (for a microprocessor with a bi-
directional reset) then a 1k (max) pull-up resistor
is recommended.
Reset Inputs (RSTIN1 & RSTIN2)
The M48T212A provides two independent inputs
which can generate an output reset. The duration
and function of these resets is identical to a reset
generated by a power cycle. Table 14 and Figure
12 illustrate the AC reset characteristics of this
function. During the time RST is enabled (t
& t
Note: RSTIN1 and RSTIN2 are each internally
pulled up to V
Calibrating the Clock
The M48T212A is driven by a quartz controlled os-
cillator with a nominal frequency of 32,768 Hz. The
devices are tested not to exceed ±35 ppm (parts
per million) oscillator frequency error at 25°C,
which equates to about ±1.53 minutes per month.
When the Calibration circuit is properly employed,
accuracy improves to better than +1/–2 ppm at
25°C.
The oscillation rate of crystals changes with tem-
perature. The M48T212A design employs periodic
counter correction. The calibration circuit adds or
subtracts counts from the oscillator divider circuit
at the divide by 256 stage, as shown in Figure 11.
The number of times pulses which are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value load-
ed into the five Calibration bits found in the Control
Register. Adding counts speeds the clock up, sub-
tracting counts slows the clock down.
The Calibration bits occupy the five lower order
bits (D4-D0) in the Control Register 8h. These bits
can be set to represent any value between 0 and
14/20
CC
CC
CC
R2HRH
SWITCH OUTPUT
falls to the power fail detect trip point, the RST
turning on a customer supplied P-Channel
), the Reset Inputs are ignored.
(see
CC
OUT
through a 100K resistor.
OUT
Figure
output.
to a separate supply when
CC
CC
should be chosen to
3).
passes V
OUT
The
switches to
OUT1
CC
PFD
Motorola
. When
R1HRH
. The
CC
(see
or
31 in binary form. Bit D5 is a Sign bit; ’1’ indicates
positive calibration, ’0’ indicates negative calibra-
tion. Calibration occurs within a 64 minute cycle.
The first 62 minutes in the cycle may, once per
minute, have one second either shortened by 128
or lengthened by 256 oscillator cycles.
If a binary ’1' is loaded into the register, only the
first 2 minutes in the 64 minute cycle will be modi-
fied; if a binary 6 is loaded, the first 12 will be af-
fected, and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibra-
tion step in the calibration register. Assuming that
the oscillator is running at exactly 32,768 Hz, each
of the 31 increments in the Calibration byte would
represent +10.7 or –5.35 seconds per month
which corresponds to a total range of +5.5 or –2.75
minutes per month.
Two methods are available for ascertaining how
much calibration a given M48T212A may require.
The first involves setting the clock, letting it run for
a month and comparing it to a known accurate ref-
erence and recording deviation over a fixed period
of time. Calibration values, including the number of
seconds lost or gained in a given period, can be
found in Application Note AN934: TIMEKEEPER
Calibration.
This allows the designer to give the end user the
ability to calibrate the clock as the environment re-
quires, even if the final product is packaged in a
non-user serviceable enclosure. The designer
could provide a simple utility that accesses the
Calibration byte.
The second approach is better suited to a manu-
facturing environment, and involves the use of the
IRQ/FT pin. The pin will toggle at 512Hz, when the
Stop bit (ST, D7 of 9h) is ’0’, the Frequency Test
bit (FT, D6 of Ch) is ’1’, the Alarm Flag Enable bit
(AFE, D7 of 6h) is ’0’, and the Watchdog Steering
bit (WDS, D7 of 7h) is ’1’ or the Watchdog Register
(7h = 0) is reset.
Any deviation from 512 Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature.
512.010124 Hz would indicate a +20 ppm oscilla-
tor frequency error, requiring a –10 (WR001010)
to be loaded into the Calibration Byte for correc-
tion. Note that setting or changing the Calibration
Byte does not affect the Frequency test output fre-
quency.
The IRQ/FT pin is an open drain output which re-
quires a pull-up resistor to V
tion. A 500-10k resistor is recommended in order
to control the rise time. The FT bit is cleared on
power-up.
For
example,
CC
for proper opera-
a
reading
of