m48t212a STMicroelectronics, m48t212a Datasheet - Page 8

• Manufacturer Part Number: m48t212a
• Description: 3.3v Timekeeper Controller
• Manufacturer: STMicroelectronics

M48T212A
Address Decoding
The M48T212A accommodates 4 address lines
(A3-A0) which allow access to the sixteen bytes of
the TIMEKEEPER clock registers. All TIMEKEEP-
ER registers reside in the controller chip itself. All
TIMEKEEPER registers are accessed by enabling
E (Chip Enable).
READ MODE
The M48T212A executes a read cycle whenever
W (Write Enable) is high and E (Chip Enable) is
low. The unique address specified by the address
inputs (A3-A0) defines which one of the on-chip
TIMEKEEPER registers is to be accessed. When
Table 11. Write Mode AC Characteristics
(T
Note: 1. C
8/20
A
t
t
WHQX
WLQZ
Symbol
= 0 to 70°C)
t
t
t
t
t
t
t
t
t
t
t
t
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
t
WLWH
WHDX
WHAX
DVWH
AVWH
AVWL
EHDX
ELEH
EHAX
DVEH
AVEH
AVAV
AVEL
(1,2)
L
(1,2)
= 5pF.
Write Cycle Time
Address Valid to Write Enable Low
Address Valid to Chip Enable Low
Write Enable Pulse Width
Chip Enable Low to Chip Enable High
Write Enable High to Address Transition
Chip Enable High to Address Transition
Input Valid to Write Enable High
Input Valid to Chip Enable High
Write Enable High to Input Transition
Chip Enable High to Input Transition
Write Enable Low to Output High-Z
Address Valid to Write Enable High
Address Valid to Chip Enable High
Write Enable High to Output Transition
Parameter
the address presented to the M48T212A is in the
range of 0h-Fh, one of the on-board TIMEKEEP-
ER registers is accessed and valid data will be
available to the eight data output drivers within
t
viding that the E and G access times are also sat-
isfied. If they are not, then data access must be
measured from the latter occurring signal (E or G)
and the limiting parameter is either t
t
When EX input is low, an external SRAM location
will be selected.
Note: Care should be taken to avoid taking both E
and EX low simultaneously to avoid bus conten-
tion.
AVQV
GLQV
after the address input signal is stable, pro-
for G rather than the address access time.
Min
85
55
60
30
30
65
65
0
0
0
0
0
0
5
M48T212A
-85
Max
25
ELQV
Unit
for E or
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns