m48t18 STMicroelectronics, m48t18 Datasheet - Page 8

• Manufacturer Part Number: m48t18
• Description: 5v, 64kbit 8 Kb X 8 Timekeeper Sram
• Manufacturer: STMicroelectronics

Operation modes
Note:
Read mode
8/30
As
oscillator of the M48T08/18/08Y are integrated on one silicon chip. The two circuits are
interconnected at the upper eight memory locations to provide user accessible
BYTEWIDE™ clock information in the bytes with addresses 1FF8h-1FFFh.
The clock locations contain the year, month, date, day, hour, minute, and second in 24 hour
BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are
made automatically. Byte 1FF8h is the clock control register. This byte controls user access
to the clock information and also stores the clock calibration setting.
The eight clock bytes are not the actual clock counters themselves; they are memory
locations consisting of BiPORT™ READ/WRITE memory cells. The M48T08/18/08Y
includes a clock control circuit which updates the clock bytes with current information once
per second. The information can be accessed by the user in the same manner as any other
location in the static memory array.
The M48T08/18/08Y also has its own Power-fail Detect circuit. The control circuitry
constantly monitors the single 5V supply for an out of tolerance condition. When V
of tolerance, the circuit write protects the SRAM, providing a high degree of data security in
the midst of unpredictable system operation brought on by low V
Battery Back-up Switchover Voltage (V
maintains data and clock operation until valid power returns.
Table 2.
1. See
X = V
The M48T08/18/08Y is in the READ Mode whenever W (WRITE Enable) is high, E1 (Chip
Enable 1) is low, and E2 (Chip Enable 2) is high. The device architecture allows ripple-
through access of data from eight of 65,536 locations in the static storage array. Thus, the
unique address specified by the 13 address inputs defines which one of the 8,192 bytes of
data is to be accessed. Valid data will be available at the Data I/O pins within address
access time (t
and G access times are also satisfied. If the E1, E2 and G access times are not met, valid
Deselect
Deselect
WRITE
READ
READ
Deselect
Deselect
Mode
Figure 4 on page 7
IH
Table 11 on page 22
or V
IL
Operating modes
V
4.75 to 5.5V
4.5 to 5.5V
AVQV
; V
PFD
V
V
V
SO
SO
or
(min)
SO
CC
) after the last address input signal is stable, providing that the E1, E2,
to
= battery back-up switchover voltage.
(1)
(1)
shows, the static memory array and the quartz-controlled clock
for details.
V
V
V
V
E1
X
X
X
IH
IL
IL
IL
V
V
V
V
SO
E2
X
X
X
IH
IH
IH
IL
), the control circuitry connects the battery which
V
V
G
X
X
X
X
X
IH
IL
V
V
V
W
X
X
X
X
IH
IH
IL
DQ0-DQ7
High Z
High Z
High Z
High Z
High Z
D
CC
D
OUT
IN
. As V
CC
Battery Back-up
CMOS Standby
falls below the
Standby
Standby
Power
Active
Active
Active
Mode
CC
is out