x1286v14zt1 Intersil Corporation, x1286v14zt1 Datasheet
x1286v14zt1
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x1286v14zt1 Summary of contents
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Data Sheet Intersil Real Time Clock/Calendar/CPU Supervisor with EEPROM FEATURES • Real Time Clock/Calendar — Tracks time in Hours, Minutes, Seconds and Hundredths of a Second — Day of the Week, Day, Month, and Year • 2 Polled Alarms ...
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PIN DESCRIPTIONS 8 LD EIAJ SOIC PHZ/IRQ Ordering Information PART NUMBER PART MARKING X1286A8* X1286A X1286A8I* X1286A I X1286V14* X1286 V X1286V14Z* (Note) X1286 VZ X1286V14I* X1286 VI X1286V14IZ* (Note) X1286 VIZ ...
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PIN ASSIGNMENTS Pin Number EIAJ SOIC TSSOP Symbol PHZ/IRQ SDA 6 9 SCL BACK X1286 Brief Description X1. ...
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ABSOLUTE MAXIMUM RATINGS Temperature Under Bias ................... -65°C to +135°C Storage Temperature......................... -65°C to +150°C Voltage and PHZ/IRQ CC BACK pin (respect to ground) ............................-0.5V to 7.0V Voltage on SCL, SDA, X1 and X2 pin (respect ...
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Notes: (1) The device enters the Active state after any start, and remains active: for 9 clock cycles if the Device Select Bits in the Slave Address Byte are incorrect or until 200nS after a stop ending a read or ...
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AC Specifications (T = -40°C to +85°C, VCC = +2.7V to +5.5V, unless otherwise specified.) A Symbol f SCL Clock Frequency SCL t Pulse width Suppression Time at inputs IN t SCL LOW to SDA Data Out Valid AA t ...
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Write Cycle Timing SCL 8th Bit of Last Byte SDA Power-up Timing Symbol (1) t Time from Power-up to Read PUR (1) t Time from Power-uppower-up to Write PUW Notes: (1) Delays are measured from the time V V slew ...
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DESCRIPTION The X1286 device is a Real Time Clock with clock/calendar, two polled alarms with integrated 32kx8 EEPROM, oscillator compensation, and battery backup switch. The oscillator uses an external, low-cost 32.768kHz crystal. All compensation and trim components are integrated on ...
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Figure 2. Recommended Crystal connection X1 X2 POWER CONTROL OPERATION The power control circuit accepts a V input. The power control circuit powers the clock from V when V < 0.2V. It will switch back to BACK CC ...
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Each register is read and written through buffers. The non-volatile portion (or the counter portion of the RTC) is updated only if RWEL is set and only after a valid write operation and stop bit. A sequential read or page ...
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Table 1. Clock/Control Memory Map Reg Addr. Type Name 7 0007 Alarm0 Y2K0 (EEPROM) 0006 DWA0 EDW0 0005 YRA0 0004 MOA0 EMO0 0003 DTA0 EDT0 0002 HRA0 EHR0 0001 MNA0 EMN0 0000 SCA0 ESC0 When there is a match, an ...
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AL1, AL0: Alarm bits—Volatile These bits announce if either alarm 0 or alarm 1 match the real time clock. If there is a match, the respective bit is set to ‘1’. The falling edge of the last data bit in ...
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INTERRUPT CONTROL AND FREQUENCY OUTPUT REGISTER (INT) Interrupt Control and Status Bits (IM, AL1E, AL0E) There are two Interrupt Control bits, Alarm 1 Interrupt Enable (AL1E) and Alarm 0 Interrupt Enable (AL0E) to specifically enable or disable the alarm interrupt ...
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WRITING TO THE CLOCK/CONTROL REGISTERS Changing any of the nonvolatile bits of the clock/ control register requires the following steps: – Write a 02h to the Status Register to set the Write Enable Latch (WEL). This is a volatile operation, ...
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Figure 4. Valid Data Changes on the SDA Bus SCL SDA Figure 5. Valid Start and Stop Conditions SCL SDA Figure 6. Acknowledge Response From Receiver SCL from Master Data Output from Transmitter Data Output from Receiver Start DEVICE ADDRESSING ...
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Figure 7. Slave Address, Word Address, and Data Bytes (128 Byte pages) Device Identifier Array CCR 0 A14 Write Operations Byte Write For a write operation, the device requires the Slave Address ...
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Figure 8. Byte Write Sequence Signals from the Master SDA Bus Signals From The Slave Figure 9. Writing 30 bytes to a 128-byte memory page starting at address 105. 7 Bytes Address = 6 Figure 10. Page Write Sequence S ...
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Acknowledge Polling Disabling of the inputs during nonvolatile write cycles can be used to take advantage of the typical 5mS write cycle time. Once the stop condition is issued to indi- cate the end of the master’s byte load operation, ...
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It should be noted that the ninth clock cycle of the read operation is not a “don’t care.” To terminate a read operation, the master must either issue a stop condi- tion during the ninth cycle or hold SDA HIGH ...
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APPLICATION SECTION CRYSTAL OSCILLATOR AND TEMPERATURE COMPENSATION Intersil has now integrated the oscillator compensation circuity on-chip, to eliminate the need for external components and adjust for crystal drift over tempera- ture and enable very high accuracy time keeping (<5ppm drift). ...
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A final application for the ATR control is in-circuit cali- bration for high accuracy applications, along with a temperature sensor chip. Once the RTC circuit is pow- ered up with battery backup, the PHZ output is set at 32.768kHz and ...
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IRQ- output which can be checked by setting an alarm for each minute. Using the pulse interrupt mode setting, the once-per-minute interrupt functions as an indication of proper oscillation. Backup Battery Operation Many types of batteries can ...
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Referring to Figure 16, Vtrip applies to the “Internal Vcc” node which powers the entire device. This means that if Vcc is powered down and the battery voltage at Vback is higher than the Vtrip voltage, then the entire chip ...
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TSSOP Package Outline Drawing NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at http://www.intersil.com/design/packages/index.asp 24 X1286 FN8101.1 April 14, 2006 ...
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... Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...