cs5373a Cirrus Logic, Inc., cs5373a Datasheet - Page 22

• Manufacturer Part Number: cs5373a
• Description: Low-power, High-performance ?? Modulator And Test Dac
• Manufacturer: Cirrus Logic, Inc.

5. OPERATIONAL MODES
The CS5373A has seven operational modes
and one sleep mode selected by the MODE2,
MODE1, and MODE0 pins.
5.1 Modulator Mode
Modulator mode (MODE 0) enables the ∆Σ
modulator and disables the DAC AC and DC
test circuitry to save power. This mode is used
for normal sensor measurements after self-
tests are completed.
5.1.1
In modulator mode (and whenever the modu-
lator is enabled) the differential analog input
signal is converted to an oversampled ∆Σ seri-
al bit stream on the MDATA output, with a
one’s density proportional to the differential
amplitude of the analog input signal.
One’s density of the MDATA output is defined
as the ratio of ‘1’ bits to total bits in the serial
22
Selection
0
1
2
3
4
5
6
7
Modulator One’s Density
MODE
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
[2:0]
Table 2. Operational Modes
Modes of Operation
Modulator: enabled.
DAC: sleep.
Modulator: enabled.
DAC: AC OUT and BUF outputs.
Modulator: enabled.
DAC: AC OUT only, BUF high-z.
Modulator: enabled.
DAC: AC BUF only, OUT high-z.
Modulator: enabled.
DAC: DC common mode output.
Modulator: enabled.
DAC: DC differential output.
Modulator: enabled.
DAC: AC common mode output.
Modulator: sleep.
DAC: sleep.
Mode Description
bit stream output, i.e. an 86% one’s density
has, on average, a ‘1’ value in 86 of every 100
output data bits. The MDATA output has a
nominal 50% one’s density for a mid-scale dif-
ferential input, approximately 86% one’s den-
sity for a positive full-scale input, and
approximately 14% one’s density for a nega-
tive full-scale input.
5.1.2
When the CS5373A modulator operates with
the CS5378 digital filter, the final decimated,
24-bit, full-scale output code range depends if
digital offset correction is enabled. With digital
offset correction enabled, amplifier offset and
the modulator internal offset are removed from
the final conversion result.
5.1.3
The modulator is designed to operate synchro-
nously with other modulators in a measure-
ment network, so a rising edge on the MSYNC
input resets the internal conversion state ma-
chine to synchronize analog sample timing.
MSYNC is automatically generated by the
CS5378 digital filter after receiving a synchro-
nization signal from the external system, and
is chip-to-chip accurate within ± 1 MCLK peri-
od.
Modulator and CS5378 Digital Filter Combination
> + (VREF + 5%)
+ VREF
0 V
- VREF
> - (VREF + 5%)
Differential Analog
Table 3. Output Coding for the CS5373A
Input Signal
Modulator
Modulator Decimated Output
Modulator Synchronization
Corrected
A2EBE0
CS5378 Digital Filter
5D1420
000000
Offset
Error Flag Possible
Error Flag Possible
Output Code
CS5373A
+100 mV
60CD40
A6A500
03B920
Offset
DS703F1