cs5378 Cirrus Logic, Inc., cs5378 Datasheet
cs5378
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cs5378 Summary of contents
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... I/O Interface and PLL: 3 5.0 V Digital Logic Core: 2 http://www.cirrus.com Description The CS5378 is a multi-function digital filter utilizing a low- power signal processing architecture to achieve efficient filtering for a delta-sigma-type modulator. By combining the CS5378 with a CS3301/02 differential amplifier, a CS5371 modulator, and a CS4373 test DAC, a synchro- nous high-resolution measurement system can be designed quickly and easily ...
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... Configuration Interface Characteristics and Specifications Specified Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Power Consumption .13 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3. System Design with CS5378 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1. Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.2. Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.3. PLL and Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.4. Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.5. System Configuration .19 3.6. Digital Filter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.7. Data Collection .19 3 ...
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... Gain Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 15.2. Offset Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 15.3. Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 16. Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 16.1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 16.2. Serial Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 16.3. Serial Data Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 17. Test Bit Stream Generator 17.1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 17.2. TBS Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 17.3. TBS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 17.4. TBS Data Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 17.5. TBS Sine Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 17.6. TBS Impulse Output .62 DS639F1 CS5378 3 ...
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... Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 24. Environmental, Manufacturing, & Handling Information . . . . . . . . . . 86 25. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 LIST OF FIGURES Figure 1. CS5378 Block Diagram Figure 2. Digital Filtering Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. FIR and IIR Coefficient Set Selection Word . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. MOSI Write Timing in SPI Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 5. MISO Read Timing in SPI Slave Mode Figure 6 ...
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... Figure 50. Test Bit Stream Gain Register TBSGAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figure 51. User Defined System Register SYSTEM1 . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Figure 52. Hardware Version ID Register VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 53. Self Test Result Register SELFTEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Figure 54. CS5378 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 LIST OF TABLES Table 1. Microcontroller and EEPROM Configuration Commands . . . . . . . . . . . . . . . . . 9 Table 2. TBS Configurations Using On-Chip Data Table 3 ...
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... Serial Interface Decimation and Filtering Engine Modulator Data Interface 1. GENERAL DESCRIPTION The CS5378 is a single channel digital filter with integrated system peripherals. Figure 1 illustrates a simplified block diagram of the CS5378. 1.1 Digital Filter Features Single channel decimation filter for CS5371 ∆Σ • ...
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... Flexible configuration options. - Configuration 'on-the-fly' via microcontrol- ler or system telemetry. - Fixed configuration via stand-alone boot EEPROM. • Low power consumption 500 SPS OWR. 100 µW standby mode. - • Flexible power supply configurations. - Separate digital logic core, telemetry I/O, CS5378 IIR2 nd 2 Order 7 ...
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... EEPROM boot sets a fixed operational con- figuration. • Configuration commands written through the serial interface. (See Table 1) - Standardized microcontroller interface us- ing SPI registers. (See Table 3) - Commands write digital filter registers and FIR / IIR filter coefficients. - Digital filter registers set hardware config- uration options. CS5378 8 ...
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... COEF SEL Use On-Chip Coefficients Operation Operation 07 - Start Digital Filter Operation CS5378 Description No Operation Write Digital Filter Register Read Digital Filter Register Write Custom FIR Coefficients Write Custom IIR Coefficients Use On-Chip Coefficients No Operation No Operation Start Digital Filter Operation ...
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... Table 2. TBS Configurations Using On-Chip Data CS5378 11:8 7:4 3:0 IIR1 FIR2 FIR1 Bits 3:0 FIR1 Coefficients 0000 Linear Phase 0001 Minimum Phase Bits 7:4 FIR2 Coefficients ...
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... Microcontroller boot Configuration Note: States of the PLL[2:0] and BOOT pins are latched immediately after reset to select modes. These pins have a weak (~100 kΩ) pull-up re- sistor enabled by default. An external 10 kΩ pull-down is required to set a low condition. CS5378 Description Description Mode Selection on Reset 11 ...
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... Ambient Operating Temperature (Power Applied) Storage Temperature Range 1. Transient currents up to 100 mA will not cause SCR latch-up. DS639F1 = 25°C. Symbol VDDCORE VDDPLL VDDPAD Industrial (-IQ) T Symbol Logic Core VDDCORE PLL VDDPLL I/O VDDPAD (Note 1) (Note 1) (Note 1) CS5378 Min Nom Max 2.375 2.5 5.25 3.135 3.3 5.25 3.135 3.3 5.25 - Min Max -0.3 6.0 -0 ...
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... V out OL t RISE t FALL t RISE t FALL (Note OUT t fa llin 0.90 * VDD 2.6 V 0.10 * VDD 0.7 V Symbol PWR 1 PWR 2 PWR 4 PWR 8 PWR S CS5378 Min Typ Max - - 135 - 50 ° -40 - +85 Min Typ Max 0.6 * VDD - VDD 0.0 - 0.8 VDD - 0.3 - VDD 0 100 - - 100 - - 100 - ...
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... MSB - Figure 5. MISO Read Timing in SPI Slave Mode Symbol LSB LSB Min Typ Max 120 - - 3 120 - - 4 120 - - 200 7 120 - - 8 120 - - 150 10 CS5378 Unit ...
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... SCK Falling to New Data Bit SCK High Time SCK Low Time Final SCK Falling to DRDY Rising DS639F1 Figure 6. Serial Data Read Timing Symbol t 5 Min Typ Max 120 2 t 120 - - 3 t 120 - - CS5378 Unit ...
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... Synchronization after SYNC rising MSYNC Setup Time to MCLK rising MCLK rising to Valid MDATA MSYNC falling to MCLK rising Notes: 3. PLL bypass mode. The PLL generates a 32.768 MHz master clock when enabled. 4. Sampling synchronization between multiple CS5378 devices receiving identical SYNC signals. DS639F1 t msh t ...
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... TBS Data Rising to MCLK Rising Setup Time MCLK Rising to TBS Data Falling Hold Time 5. TBSDATA can be delayed from full bit periods. The timing diagram shows no TBSDATA delay. DS639F1 t 1 Figure 8. TBS Output Data Timing Symbol t 1 (Note CS5378 t 2 Min Typ Max Unit - 256 - kbps 60 - ...
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... Other system devices default to a power- down state when the CS5378 is reset. 3.3 PLL and Clock Generation A PLL is included on the CS5378 to generate an in- ternal 1.024 MHz, 2.048 MHz, or 4.096 MHz standard clock or manchester encoded input. Clock inputs for other system devices are driven by clock out- puts from the CS5378 ...
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... General Purpose I/O (GPIO) Eight general purpose pins are available on the CS5378 for system control. Each pin can be set as input or output, high or low, with an internal pull- up enabled or disabled. The CS3301/02, CS5371 and CS4373 devices in Figure 9 are configured by simple pin settings controlled through the CS5378 GPIO pins ...
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... PLL (VDDPLL). The I/O pin power supplies determine the maximum input and output voltages when interfacing to peripherals, the logic core pow- er supply largely determines the power consump- tion of the CS5378 and the PLL power supply powers the internal PLL circuitry. 4.1 Pin Descriptions VDDPAD, GNDPAD - Pins 9, 10 Sets the interface voltage to a microcontroller, sys- tem telemetry, modulator, and test DAC ...
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... Configuration commands and data are encoded in the EEPROM as specified in the ‘Configuration By EEPROM’ section of this data sheet, starting on page 25. Microcontroller Boot When the BOOT pin is low after reset, the CS5378 enters an idle state waiting for a microcontroller to Fail write configuration commands and initialize filter Code operation ...
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... MHz master clock, or the CS5378 PLL can create a synchronous 32.768 MHz clock from a slower clock. To ensure the generated clock re- mains synchronous with the network, the CS5378 PLL uses a phase/frequency detector architecture ...
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... DS639F1 Jitter on the input clock causes jitter in the generat- ed modulator clock, resulting in sample timing er- rors and increased noise. Skew between input clocks from node to node cre- ates a sample timing offset, resulting in systematic measurement errors in a reconstructed signal. CS5378 23 ...
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... The CS5378 has a dedicated SYNC input that aligns the internal digital filter phase and generates an external signal for synchronizing modulator an- alog sampling. By providing simultaneous rising edges to the SYNC pins of multiple CS5378 devic- es, synchronous sampling across a network can be guaranteed. 7.1 Pin Description SYNC - Pin 19 Synchronization input, rising edge triggered ...
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... CONFIGURATION BY EEPROM After reset, the CS5378 reads the state of the GPIO7:BOOT pin to determine a source for con- figuration commands. If BOOT is high, the CS5378 initiates serial transactions to read config- uration information from an external EEPROM. 8.1 Pin Descriptions Pins required for EEPROM boot are listed here, other serial pins are inactive ...
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... DS639F1 Address ADDR[15:0] Read data beginning at the address given in ADDR. READ 2 BYTE CMD ADDR 0x03 ADDR ADDR Figure 15. EEPROM Serial Read Transactions Definition DATA1 DATA2 DATA3 1 BYTE / 3 BYTE DATA LSB 2 1 LSB X CS5378 26 ...
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... The IIR co- efficient write order is: a11, b10, b11, a21, a22, b20, b21, and b22. See “IIR Filter” on page 52 for more information about IIR filter coefficients. CS5378 27 ...
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... Write Digital Filter Register DATA 02 NUM FIR1 Write Custom FIR Coefficients NUM FIR2 (FIR COEF) 03 a11 Write Custom IIR Coefficients b10 b11 a21 a22 b20 b21 b22 04 COEF SEL Use On-Chip Coefficients Operation Operation 07 - Start Digital Filter Operation CS5378 Description 28 ...
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... Example EEPROM Configuration Table 8 shows an example EEPROM file for a min- imal CS5378 configuration. Addr Data Description 00 00 Mfg header Write ROM Coefficients ...
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... Microcontroller serial transactions require toggling the SS:EECS pin as the CS5378 chip select and writing a serial clock to the SCK input. Serial data is input to the CS5378 on the MOSI pin, and output on the MISO pin. 9.3 Microcontroller Serial Transactions Microcontroller configuration commands are writ- ten to the digital filter through SPI registers ...
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... Write SPI registers beginning at the address in ADDR. ADDR[7:0] Read SPI registers beginning at the address in ADDR. 0x02 ADDR Data1 Data2 0x03 ADDR Data1 Figure 18. Microcontroller Serial Transactions CS5378 Definition DataN Data2 DataN LSB 2 1 LSB X 31 ...
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... There must be a small delay between transactions for the CS5378 to process the incoming data. Two methods can be used to ensure the CS5378 is ready to receive the next configuration command. 1) Delay a fixed 1 ms period to guarantee enough time for the command to be completed. ...
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... COEF SEL - 000006 - - 000007 - - 000008 - - 000009 - - CS5378 Description No Operation Write Digital Filter Register Read Digital Filter Register Write Custom FIR Coefficients Write Custom IIR Coefficients Use On-Chip Coefficients No Operation No Operation Start Digital Filter Operation Stop Digital Filter Operation 33 ...
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... Delay poll E2DREQ Filter Stop - 0x09 This command disables the digital filter. Measure- ment data output stops immediately after this com- mand is issued. No data words are required for this command. Sample Command Delay poll E2DREQ CS5378 34 ...
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... Example Microcontroller Configuration Table 10 shows an example microcontroller transactions for a minimal CS5378 configuration. Transaction Table 10. Example Microcontroller Configuration DS639F1 SPI Data Delay 1ms or poll E2DREQ Delay 1ms or poll E2DREQ ...
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... MFLAG 512 kHz DC Offset & Gain Correction 10. MODULATOR INTERFACE The CS5378 performs digital filtering for a ∆Σ type modulator. Signals from the ∆Σ modulators are connected through the modulator data interface (MDI). 10.1 Pin Descriptions MCLK - Pin 11 Modulator clock output. Nominally 2.048 MHz or 1 ...
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... MFLAG signal is cleared. The MFLAG input is mapped to a status bit in the serial data output stream, and is associated with each sample when written. See “Serial Data Inter- face” on page 58 for more information on the MFLAG error bit in the serial data status byte. CS5378 37 ...
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... DC Offset & Gain Correction 11. DIGITAL FILTER INITIALIZATION The CS5378 digital filter consists of three multi- stage sections: a three stage SINC filter, a two stage FIR filter, and a two stage IIR filter. To initialize the digital filter, FIR and IIR coeffi- cient sets are selected using configuration com- ...
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... Standby Mode The CS5378 can be placed in a low-power standby mode by sending the ‘Filter Stop’ configuration command and programming the digital filter clock to 32 kHz. In this mode the digital filter idles, con- suming minimal power until re-enabled by later configuration commands ...
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... The SINC filter is synchronized to the external sys- tem by the MSYNC signal, which is generated from the SYNC input. The MSYNC signal sets a reference time (time 0) for all filter operations, and the SINC filter is restarted to phase align with this reference time. CS5378 6th order sinc2 sinc2 stage3 stage4 ...
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... SINC2 Deci- Deci- Stages mation mation 3 2,3 1,2,3 2,3 1,2,3 3 1,2,3 3 2,3 3 1,2,3 3 2,3 1,2,3 1,2,3,4 Table 11. SINC Filter Configurations CS5378 SINC3 SINC3 Deci- Stages mation 4,7 4 5,7 20 3,5,7 20 3,5,7 50 3,4,7 20 3,5,7 100 2,3,5,7 100 2,3,5,7 100 2,3,5,7 500 1,2,3,5,7 41 ...
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... − − 1 ⎝ ⎠ Table 12. SINC1 and SINC2 Filter Coefficients CS5378 Filter Coefficients 2460 2380 2226 2010 ...
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... − − 1 ⎝ ⎠ Table 13. SINC3 Filter Coefficients CS5378 = ...
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... Figure 26 and Table 14. Which on-chip coefficient set to use is selected by a data word following the ‘Write ROM Coeffi- cients’ configuration command. See “Filter Coef- ficient Selection” on page 38 for information about selecting on-chip coefficient sets. CS5378 44 ...
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... Custom filter sets should normalize the maximum coefficient value to 24-bit two’s complement full scale, 0x7FFFFF, and scale all other coefficients accordingly. To maintain maximum internal dy- namic range, the CS5378 FIR filter performs dou- ble precision calculations with an automatic gain correction to scale the final output. DS639F1 Custom FIR coefficients are uploaded using the ‘ ...
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... Table 14. FIR Filter Characteristics CS5378 Passband Stopband Ripple Atten- ( ± dB) uation (dB) 0.0042 130.38 0.0045 130.38 0.0040 130.42 0.0041 130.42 0.0080 130.45 0.0064 130.43 0.0043 130 ...
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... Table 15. SINC + FIR Group Delay CS5378 Group Delay (Input Rate) 17.5 7 3.0 8.5 19.0 40.0 7 3.0 6.0 8.5 25.0 50.5 133.0 260.5 1310.5 23.5 See Figure 62.5 See Figure FIR2 Output ...
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... Minimum phase group delay FIR1 Minimum Phase Group Delay (Normalized frequency) FIR2 Minimum Phase Group Delay (Normalized frequency) DS639F1 Table 16. Minimum Phase Group Delay CS5378 48 ...
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... Figure 27. FIR1 Coefficients CS5378 h = 8388607 7042723 4768946 2266428 189436 -1053303 -1392827 -1084130 -496361 39864 ...
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... Figure 28. FIR2 Linear Phase Coefficients CS5378 h = 8388607 3875315 -766230 -1854336 -137179 1113788 454990 -642475 -553873 71 h ...
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... Figure 29. FIR2 Minimum Phase Coefficients CS5378 h = 67863 -190800 -128546 114197 147750 -46352 -143269 -13290 114721 71 h ...
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... The characteristic equations for the 2nd order IIR include an input value output value, Y, and three intermediate values, W3, W4, and W5, each separated by a delay element (z CS5378 ...
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... Custom filter sets should normalize the coefficients to 24-bit two’s complement full scale, 0x7FFFFF. To maintain maximum internal dynamic range, the CS5378 IIR filter performs double precision calculations with an automatic gain correction to scale the final output. Custom IIR coefficients are uploaded using the ‘ ...
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... Table 16. IIR Filter Characteristics CS5378 ( 2000 SPS 1000 SPS 500 SPS 333 SPS 250 SPS 2000 SPS 1000 SPS 500 SPS) ...
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... − − ⎝ Table 17. IIR Filter Coefficients CS5378 Filter Coefficients (normalized 24-bit -8309916 8349262 -8349262 -8231957 8310282 -8310282 -8078179 8233393 -8233393 -7927166 ...
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... Correction Correction Offset Calibration 15. GAIN AND OFFSET CORRECTION The CS5378 digital filter can apply gain and offset corrections to the measurement data. Also, an off- set calibration algorithm can automatically calcu- late the offset correction value. A gain correction value is written to the GAIN reg- isters (0x21), while an offset correction value is written to the OFFSET register (0x25) ...
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... Once the OFFSET register is written, the USEOR bit in the FILTCFG register enables offset correc- tion. 15.3 Offset Calibration An offset calibration algorithm in the CS5378 can automatically calculate an offset correction value. When using the offset calibration algorithm, back- ground noise data should be used as the input signal for calculating the offset of the measurement chan- nel ...
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... MFLAG Bit - MFLAG The MFLAG bit is set in the status byte when an signal is received on the MFLAG pin. When re Status -- -- -- Figure 34. 32-bit Serial Data Format CS5378 DRDY SCK MISO 0 Data FIFO Time Break 1 - FIFO Overflow 1 - Time Break CS5378 58 ...
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... Conver- sion data is 24-bit two’s complement format. 16.3 Serial Data Transactions The CS5378 automatically initiates serial data transactions whenever data becomes available in the output FIFO by driving the DRDY pin low. Once a serial data transaction is initiated, serial clocks received into SCK cause data to be output to MISO, as shown in Figure 35 ...
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... Figure 36. Test Bit Stream Generator Block Diagram 17. TEST BIT STREAM GENERATOR The CS5378 test bit stream (TBS) generator creates sine wave or impulse ∆Σ bit stream data to drive an external test DAC. The TBS digital output can also be internally connected to the MDATA inputs for loopback testing of the digital filter ...
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... Maximum 0x04FFFF, nominal 0x04B000. 17.4 TBS Data Source An on-chip 24-bit 1024 point digital sine wave is stored on the CS5378 which will produce the test signal frequencies listed in Table 18. Additional discrete test frequencies and output rates can be programmed by varying the interpolation factor and output rate ...
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... TIMEB pin, a single positive TBSGAIN value is written to the TBS generator to create the impulse. 17.7 TBS Loopback Testing Included as part of the CS5378 test bit stream gen- erator is a feedback path to the digital filter MDA- TA input. This loopback mode provides a fully digital signal path to test the TBS generator, digital ...
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... Step Input and Group Delay A simple method to empirically measure the step response and group delay of a CS5378 measure- ment channel is to use the time break signal as both a timing reference input and an analog step input. When a rising edge is received on the TIMEB pin ...
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... GP_DIR direction bits to control the pin value. This open-drain output configuration uses the internal pull-up resistor to hold the pin high when GP_DIR is set as an input, and drives the pin low when GP_DIR is set as an output. CS5378 R GPIO 64 ...
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... If a pin in output mode is written as a logical 1, the CS5378 attempts to drive the pin high external device forces the pin DS639F1 low, the read value reflects the pin state and returns a logical 0 ...
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... REGISTER SUMMARY 20.1 SPI Registers The CS5378 SPI registers interface the serial port to the digital filter. Name Addr. SPICTRLH 00 SPICTRLM 01 SPICTRLL 02 SPICMDH 03 SPICMDM 04 SPICMDL 05 SPIDAT1H 06 SPIDAT1M 07 SPIDAT1L 08 SPIDAT2H 09 SPIDAT2M 0A SPIDAT2L 0B DS639F1 Type # Bits R/W 8 SPI Control Register, High Byte R/W 8 SPI Control Register, Middle Byte ...
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... SPI mode fault flag 7:0 14:13 -- reserved 12 EMOP External master to SPI operation in progress flag 11 SWEF SPI write collision error flag 10:9 -- reserved 8 E2DREQ External master to digital filter request flag CS5378 16 SPI Address: 0x00 -- 0x01 R/W 0x02 1 -- Not defined; read Readable E2DREQ W Writable R/W R/W Readable and ...
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... R SCMD4 SCMD3 SCMD2 SCMD1 R/W R/W R/W R 15:8 SCMD[15:8] SPI Command Mid- dle Byte CS5378 16 SPI Address: 0x03 SCMD16 0x04 R/W 0x05 0 -- Not defined; read Readable SCMD8 W Writable R/W R/W Readable and 0 Writable (LSB) 0 Bits in bottom rows SCMD0 are reset condition ...
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... R/W R SDAT4 SDAT3 SDAT2 SDAT1 R/W R/W R/W R 15:8 SDAT[15:8] SPI Data Middle Byte CS5378 16 SPI Address: 0x06 SDAT16 0x07 R/W 0x08 0 -- Not defined; read Readable SDAT8 W Writable R/W R/W Readable and 0 Writable (LSB) 0 Bits in bottom rows SDAT0 are reset condition ...
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... R/W R SDAT4 SDAT3 SDAT2 SDAT1 R/W R/W R/W R 15:8 SDAT[15:8] SPI Data Middle Byte CS5378 16 SPI Address: 0x09 SDAT16 0x0A R/W 0x0B 0 -- Not defined; read Readable SDAT8 W Writable R/W R/W Readable and 0 Writable (LSB) 0 Bits in bottom rows SDAT0 are reset condition ...
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... Digital Filter Registers The CS5378 digital filter registers control hardware peripherals and filtering functions. Name Addr. CONFIG 00 RESERVED 01-0D GPCFG 0E RESERVED 0F-1F FILTCFG 20 GAIN 21 RESERVED 22-24 OFFSET 25 RESERVED 26-28 TIMEBRK 29 TBSCFG 2A TBSGAIN 2B SYSTEM1 2C SYSTEM2 2D VERSION 2E SELFTEST 2F DS639F1 Type # Bits R/W 24 Hardware Configuration R/W 24 Reserved R/W 24 GPIO[7:0] Direction, Pull-Up Enable, and Data ...
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... MCKFS MCLK frequency select [2:0] 111: reserved 110: reserved 101: 4.096 MHz 100: 2.048 MHz 011: 1.024 MHz 010: 512 kHz 001: reserved 000: reserved CS5378 16 DF Address: 0x00 DFS0 R/W -- Not defined; 1 read Readable 8 W Writable MCKFS0 R/W Readable and ...
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... R GP_DATA4 GP_DATA3 GP_DATA2 GP_DATA1 R/W R/W R/W R 15:8 GP_PULL GPIO pullup resistor [7:0] 1: Enabled 0: Disabled CS5378 16 DF Address: 0x0E GP_DIR0 R/W -- Not defined; read Readable W Writable 8 R/W Readable and GP_PULL0 Writable R/W 1 Bits in bottom rows are reset condition (LSB) 0 GP_DATA0 R/W 1 7:0 GP_DATA ...
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... FSEL[2:0] Output filter stage select 111: reserved 110: reserved 101: IIR 3rd Order 100: IIR 2nd Order 011: IIR 1st Order 010: FIR2 Output 001: FIR1 Output 000: SINC Output CS5378 16 DF Address: 0x20 EXP0 R/W -- Not defined; read Readable ...
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... GAIN9 R/W R/W R/W R GAIN4 GAIN3 GAIN2 GAIN1 R/W R/W R/W R 15:8 GAIN[15:8] Gain Correction Middle Byte CS5378 16 DF Address: 0x21 GAIN16 R/W -- Not defined; read Readable W Writable 8 R/W Readable and GAIN8 Writable R/W 0 Bits in bottom rows are reset condition (LSB) 0 GAIN0 R/W 0 15:8 GAIN[7:0] ...
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... R/W R/W R/W R OFST4 OFST3 OFST2 OFST1 R/W R/W R/W R 15:8 OFST[15:8] Offset Correction Middle Byte CS5378 16 DF Address: 0x25 OFST16 R/W -- Not defined; read Readable W Writable 8 R/W Readable and OFST8 Writable R/W 0 Bits in bottom rows are reset condition (LSB) 0 OFST0 R/W 0 15:8 OFST[7:0] Offset Correction ...
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... R/W R/W R/W R TBRK4 TBRK3 TBRK2 TBRK1 R/W R/W R/W R 15:8 TBRK[15:8] Time Break Counter Middle Byte CS5378 16 DF Address: 0x29 TBRK16 R/W -- Not defined; read Readable W Writable 8 R/W Readable and TBRK8 Writable R/W 0 Bits in bottom rows are reset condition (LSB) 0 TBRK0 R/W 0 15:8 TBRK[7:0] ...
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... MHz 110: 1.024 MHz 101: 512 kHz 100: 256 kHz 011: 128 kHz 010: 64 kHz 001: 32 kHz 000: 4 kHz 11 TSYNC Synchronization 1: Sync enabled 0: No sync 10:8 -- reserved CS5378 16 DF Address: 0x2A INTP0 R/W -- Not defined; read Readable W Writable 8 R/W Readable and ...
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... TGAIN4 TGAIN3 TGAIN2 TGAIN1 R/W R/W R/W R 15:8 TGAIN[15:8] Test Bit Stream Gain Middle Byte CS5378 16 DF Address: 0x2B TGAIN16 R/W -- Not defined; read Readable W Writable 8 R/W Readable and TGAIN8 Writable R/W 0 Bits in bottom rows are reset condition (LSB) 0 TGAIN0 ...
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... R/W R SYS4 SYS3 SYS2 SYS1 R/W R/W R/W R 15:8 SYS[15:8] System Register 15:8 Middle Byte CS5378 16 DF Address: 0x2C SYS16 R/W -- Not defined; read Readable W Writable 8 R/W Readable and SYS8 Writable R/W 0 Bits in bottom rows are reset condition (LSB) 0 SYS0 R/W 0 SYS[7:0] System Register ...
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... R/W R/W R ROM4 ROM3 ROM2 ROM1 R/W R/W R/W R 15:8 HW Hardware Revision 7:4 [7: CS5378 Rev A CS5378 16 DF Address: 0x2E TYPE0 R/W -- Not defined; read Readable W Writable 8 R/W Readable and HW0 Writable R/W 1 Bits in bottom rows are reset condition (LSB) 0 ROM0 R/W 1 ROM ROM Version [7: Ver 1 ...
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... PROM1 R/W R/W R/W R 15:12 DRAM Data RAM Test [3:0] ‘A’: Pass ‘F’: Fail 11:8 PRAM Program RAM Test [3:0] ‘A’: Pass ‘F’: Fail CS5378 16 DF Address: 0x2F EU0 R/W -- Not defined; read Readable W Writable 8 R/W Readable and PRAM0 Writable R/W 0 Bits in bottom rows ...
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... MDATA 13 16 GNDPLL MFLAG 14 15 VDDPLL Figure 54. CS5378 Pin Assignments Pin Type General Purpose Input / Output Input / Output Input / Output General Purpose I/O with PLL mode select. GPIO pins have weak (~100 kΩ) internal pullups. PLL mode selection latched immediately after reset. ...
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... Input / Output Serial data, master out / slave in. Input Slave select with EEPROM chip select, active low. Power Supplies Supply Supply Supply CS5378 Pin Description Modulator clock output. Modulator sync output. Modulator data input. Modulator flag input. Clock input. Reset, active low. ...
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... SEATING PLANE SIDE VIEW NOM MAX MIN -- 0.084 -- 0.006 0.010 0.05 0.069 0.074 1.62 -- 0.015 0.22 0.413 9.90 0.307 0.323 7.40 0.209 0.220 5.00 0.026 0.030 0.55 0.041 0.63 4° 8° 0° JEDEC #: MO-150 Controlling Dimension is Millimeters CS5378 1 E1 ∝ END VIEW L MILLIMETERS NOM MAX -- 2.13 0.15 0.25 1.75 1.88 -- 0.38 10.20 10.50 7.80 8.20 5.30 5.60 0.65 0.75 0.90 1.03 4° 8° NOTE 2 ...
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... INFORMATION Model CS5378-IS CS5378-ISZ Lead Free 24.ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS5378-IS CS5378-ISZ Lead Free * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 25.REVISION HISTORY Revision Date PP1 FEB 2004 Initial “Preliminary Product” release. F1 OCT 2005 Added lead-free device ordering information. Added MSL data. ...