cs5378 Cirrus Logic, Inc., cs5378 Datasheet - Page 16

• Manufacturer Part Number: cs5378
• Description: Low-power Single-channel Decimation Filter
• Manufacturer: Cirrus Logic, Inc.

SWITCHING CHARACTERISTICS
CLK, SYNC, MCLK, MSYNC, and MDATA
Notes: 3. PLL bypass mode. The PLL generates a 32.768 MHz master clock when enabled.
DS639F1
Master Clock Frequency
Master Clock Duty Cycle
Master Clock Rise Time
Master Clock Fall Time
Master Clock Jitter
Synchronization after SYNC rising
MSYNC Setup Time to MCLK rising
MCLK rising to Valid MDATA
MSYNC falling to MCLK rising
SYNC
MCLK
MSYNC
MDATA
4. Sampling synchronization between multiple CS5378 devices receiving identical SYNC signals.
Note: SYNC input latched on MCLK rising edge. MSYNC output triggered by MCLK falling edge.
t
t
msd
msh
Parameter
Figure 7. SYNC, MCLK, MSYNC, MDATA Interface Timing
= T
= T
f
MCLK
MCLK
MCLK
t
msd
/ 4
t
msh
t
t
msd
msh
2.048 MHz
(Note 3)
(Note 4)
= 122 ns
= 488 ns
t
Symbol
msd
SYNC
t
t
DTY
CLK
JTR
t
t
RISE
FALL
t
mss
mdv
msf
Data1
t
t
msd
msh
Min
1.024 MHz
32
40
20
20
-2
-
-
-
-
= 244 ns
= 976 ns
32.768
Typ
-
-
-
-
-
-
-
-
Max
300
Data2
33
60
20
20
75
2
-
-
CS5378
MHz
Unit
µs
ns
ns
ps
ns
ns
ns
%
16