cs5378 Cirrus Logic, Inc., cs5378 Datasheet - Page 22

• Manufacturer Part Number: cs5378
• Description: Low-power Single-channel Decimation Filter
• Manufacturer: Cirrus Logic, Inc.

6. PLL AND CLOCK GENERATION
The CS5378 requires a 32.768 MHz master clock,
which can be supplied directly or from an internal
phase locked loop. This master clock is used to
generate an internal digital filter clock and an exter-
nal modulator clock.
The internal PLL will lock to standard clock or
manchester encoded input signals. The input type
and input frequency are selected by the reset state
of the PLL mode select pins.
6.1 Pin Descriptions
CLK - Pin 17
Clock or PLL input, standard clock or manchester.
GPIO[4:6]:PLL[0:2] - Pins 5, 6, 7
PLL mode select, latched immediately after reset.
Weak (~100 kΩ) internal pull-ups default high, ex-
ternal 10 kΩ pull-downs required to set low.
6.2 PLL Mode Select
The CS5378 PLL operational mode and frequency
are selected immediately after reset based on the
state of the PLL[0:2] pins. On the rising edge of the
reset signal, the digital high or low state of the
PLL[0:2] pins is latched and used to program the
clock input type and frequency.
DS639F1
PLL[2:0]
CLK
PLL
Figure 12. Clock Generation Block Diagram
32.768
MHz
DSPCFG Register
Clock Divider
and MCLK
Generator
A weak internal pull-up resistor (~100 kΩ) will
hold the PLL mode select pins high by default. To
force the pin low on reset, an external 10 kΩ pull-
down resistor should be connected. Once the pin
state is latched following reset, the GPIO[4:6] pins
funtion without affecting PLL operation.
6.3 Synchronous Clocking
To guarantee synchronous measurements through-
out a sensor network, a system clock should be dis-
tributed to arrive at all nodes in phase.
distributed system clock can either be the full
32.768 MHz master clock, or the CS5378 PLL can
create a synchronous 32.768 MHz clock from a
slower clock. To ensure the generated clock re-
mains synchronous with the network, the CS5378
PLL uses a phase/frequency detector architecture.
111
110
101
100
011
010
001
000
PLL[2:0]
Table 5. PLL Mode Selections
32.768 MHz clock input (PLL bypass).
1.024 MHz clock input.
2.048 MHz clock input.
4.096 MHz clock input.
32.768 MHz clock input (PLL bypass).
1.024 MHz manchester input.
2.048 MHz manchester input.
4.096 MHz manchester input.
PLL Mode
Internal
Clocks
MCLK
Output
CS5378
The
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