adc1213d125hn/c1 NXP Semiconductors, adc1213d125hn/c1 Datasheet - Page 14
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adc1213d125hn/c1
Manufacturer Part Number
adc1213d125hn/c1
Description
Dual 12-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps
Manufacturer
NXP Semiconductors
Datasheet
1.ADC1213D125HNC1.pdf
(41 pages)
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NXP Semiconductors
ADC1213D_SER_5
Preliminary data sheet
14.1.2 Anti-kickback circuitry
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
Anti-kickback circuitry (RC filter in
charge injection generated by the sampling capacitance.
The RC filter is also used to filter noise from the signal before it reaches the sampling
stage. The value of the capacitor should be chosen to maximize noise attenuation without
degrading the settling time excessively.
The component values are determined by the input frequency and should be selected so
as not to affect the input bandwidth.
Fig 6.
Fig 7.
Input sampling circuit
Anti-kickback circuit
INAM
INBM
INAP
INBP
All information provided in this document is subject to legal disclaimers.
1, 14
2, 13
Rev. 05 — 23 April 2010
Package
Figure
ESD
R
R
7) is needed to counteract the effects of a
Parasitics
005aaa073
C
ADC1213D series
INM
INP
R on = 15 Ω
R on = 15 Ω
Internal
Internal
Switch
Switch
clock
clock
4 pF
4 pF
C s
C s
005aaa069
ADC1213D series
© NXP B.V. 2010. All rights reserved.
14 of 41
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