adc12d040civsx National Semiconductor Corporation, adc12d040civsx Datasheet - Page 19

• Manufacturer Part Number: adc12d040civsx
• Description: Dual 12-bit, 40 Msps, 600 Mw A/d Converter With Internal/external Reference And Sample-and-hold
• Manufacturer: National Semiconductor Corporation

Applications Information
4.0 POWER SUPPLY CONSIDERATIONS
The power supply pins should be bypassed with a 10 µF
capacitor and with a 0.1 µF ceramic chip capacitor within a
centimeter of each power pin. Leadless chip capacitors are
preferred because they have low series inductance.
As is the case with all high-speed converters, the
ADC12D040 is sensitive to power supply noise. Accordingly,
the noise on the analog supply pin should be kept below 100
mV
No pin should ever have a voltage on it that is in excess of
the supply voltages, not even on a transient basis. Be espe-
cially careful of this during turn on and turn off of power.
The V
be operated from a supply in the range of 2.35V to V
(nominal 5V). This can simplify interfacing to low voltage
devices and systems. Note, however, that t
reduced V
higher than V
P-P
DR
.
pin provides power for the output drivers and may
DR
. DO NOT operate the V
D
.
DR
FIGURE 6. Example of a Suitable Layout
OD
pin at a voltage
(Continued)
increases with
D
19
5.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are es-
sential to ensure accurate conversion. Maintaining separate
analog and digital areas of the board, with the ADC12D040
between these areas, is required to achieve specified per-
formance.
The ground return for the data outputs (DR GND) carries the
ground current for the output drivers. The output current can
exhibit high transients that could add noise to the conversion
process. To prevent this from happening, the DR GND pins
should NOT be connected to system ground in close prox-
imity to any of the ADC12D040’s other ground pins.
Capacitive coupling between the typically noisy digital cir-
cuitry and the sensitive analog circuitry can lead to poor
performance. The solution is to keep the analog circuitry
separated from the digital circuitry, and to keep the clock line
as short as possible.
The effects of the noise generated from the ADC output
switching can be minimized through the use of 100Ω resis-
tors in series with each data output line. Locate these resis-
tors as close to the ADC output pins as possible.
20046016
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