adc122s655cimmx National Semiconductor Corporation, adc122s655cimmx Datasheet - Page 16

• Manufacturer Part Number: adc122s655cimmx
• Description: Adc122s655 Dual 12-bit, 200 Ksps To 500 Ksps, Simultaneous Sampling A/d Converter
• Manufacturer: National Semiconductor Corporation

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seen as the first falling edge of SCLK. In the third condition,
CS and SCLK go low simultaneously and the ADC122S655
immediately enters acquisition mode. While there is no timing
restriction with respect to the falling edges of CS and the
falling edge of SCLK, see Figure 5 for setup and hold time
requirements for the falling edge of CS with respect to the
rising edge of SCLK.
3.1 CS Input
The CS (chip select bar) is an active low input that is TTL and
CMOS compatible. The ADC122S655 transitions from acqui-
sition mode, to conversion mode, to power-down mode when
CS is low and is always in power-down mode when CS is high.
The falling edge of CS marks the beginning of a conversion
where the input to Channel A and Channel B are tracked by
the input sampling capacitor. The rising edge of CS marks the
end of a conversion window. As a result, CS frames the con-
version window and can be used to control the sample rate of
the ADC122S655. While the SCLK frequency is limited to a
range of 6.4 MHz to 16 MHz, the frequency of CS has no
limitation. This allows a system designer to operate the
ADC122S655 at sample rates approaching zero samples per
second if conserving power is very important. See Burst Mode
Operation for more details. Multiple conversions can occur
within a given conversion frame with each conversion requir-
ing thirty-two SCLK cycles. This is referred to as continuous
conversion mode and is shown in Figure 2 of the Timing Di-
agram section.
Proper operation requires that the fall of CS not occur simul-
taneously with a rising edge of SCLK. If the fall of CS occurs
during the rising edge of SCLK, the data might be clocked out
one bit early. Whether or not the data is clocked out early
depends upon how close the CS transition is to the SCLK
transition, the device temperature, and characteristics of the
individual device. To ensure that the MSB is always clocked
out at a given time (the 5th falling edge of SCLK), it is essential
that the fall of CS always meet the timing requirement speci-
fied in the Timing Specification table.
3.2 SCLK Input
The SCLK (serial clock) serves two purposes in the
ADC122S655. It is used by the ADC122S655 as the conver-
sion clock and it is used as the serial clock to output the
conversion results. The SCLK input is TTL and CMOS com-
patible. Internal settling time requirements limit the maximum
clock frequency while internal capacitor leakage limits the
minimum clock frequency. The ADC122S655 offers guaran-
teed performance with the clock rates indicated in the Elec-
trical Characteristics Table.
3.3 Data Output(s)
The conversion result of Channel A and Channel B is output
on D
result of Channel B. The data output format of the
ADC122S655 is binary, two’s complement, as shown in Table
2. This table indicates the ideal output code for a given input
voltage and does not include the effects of offset, gain error,
linearity errors, or noise. Each data output bit is output on the
falling edges of SCLK.
OUT
, with the result of Channel A being output before the
16
While data is output on the falling edges of SCLK, receiving
systems have the option of capturing the data from the
ADC122S655 on the subsequent rising or falling edge of
SCLK. If a receiving system is going to capture data on the
subsequent falling edges of SCLK, it is important to make sure
that the minimum hold time after an SCLK falling edge (t
is acceptable. See Figure 4 for D
D
rising edge of CS. If CS is raised prior to the 16th falling edge
of SCLK, the current conversion is aborted and D
into its high impedance state. A new conversion will begin
when CS is taken LOW.
Applications Information
OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC122S655:
−40°C
+4.5V
1V
6.4 MHz
V
4.0 POWER CONSUMPTION
The architecture, design, and fabrication process allow the
ADC122S655 to operate at conversion rates up to 500 kSPS
while consuming very little power. The ADC122S655 con-
sumes the least amount of power while operating in power
down mode. For applications where power consumption is
critical, the ADC122S655 should be operated in power down
mode as often as the application will tolerate. To further re-
duce power consumption, stop the SCLK while CS is high.
4.1 Burst Mode Operation
Normal operation of the ADC122S655 requires the SCLK fre-
quency to be thirty-two times the sample rate and the CS rate
to be the same as the sample rate. However, in order to min-
imize power consumption in applications requiring sample
rates below 200 kSPS, the ADC122S655 should be run with
an SCLK frequency of 16 MHz and a CS rate as slow as the
system
ADC122S655 is operating in burst mode. The ADC122S655
enters into power down mode at the end of each conversion,
minimizing power consumption. This causes the converter to
spend the longest possible time in power down mode. Since
power consumption scales directly with conversion rate, min-
imizing power consumption requires determining the lowest
conversion rate that will satisfy the requirements of the sys-
tem.
−V
CM
OUT
V
Analog Input
0V − 1.5 LSB
(+IN) − (−IN)
REF
≤
REF
: See Section 2.3
+ 0.5 LSB
− 0.5 LSB
TABLE 2. Ideal Output Code vs. Input Voltage
is enabled on the falling edge of CS and disabled on the
V
≤
≤
REF
− 1.5 LSB 0111 1111 1111
+ 0.5 LSB 1000 0000 0000
V
≤
T
requires.
A
A
≤
f
SCLK
≤
≤
V
+5.5V
+105°C
A
≤
16 MHz
0000 0000 0001
0000 0000 0000
1111 1111 1111
Binary Output
Complement
When
2's
this
OUT
is
hold and access times.
Hex Code
Comp.
accomplished,
FFF
7FF
001
000
800
2's
Dec Code
OUT
Comp.
−2048
2047
2's
−1
1
0
will go
DH
the
)