adc12c105eb National Semiconductor Corporation, adc12c105eb Datasheet - Page 7

• Manufacturer Part Number: adc12c105eb
• Description: 12-bit, 95/105 Msps A/d Converter
• Manufacturer: National Semiconductor Corporation

C
DIGITAL OUTPUT CHARACTERISTICS (D0–D13, DRDY)
V
V
+I
−I
C
POWER SUPPLY CHARACTERISTICS
I
I
t
t
t
t
t
t
t
t
Symbol
A
DR
CH
CL
CONV
OD
SU
H
AD
AJ
OUT(1)
OUT(0)
Symb
IN
OUT
SC
SC
Timing and AC Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V
+1.2V, f
measurements are taken at 50% of the signal amplitude. Boldface limits apply for T
T
A
= 25°C (Notes 8, 9)
CLK
Digital Input Capacitance
Logical “1” Output Voltage
Logical “0” Output Voltage
Output Short Circuit Source Current
Output Short Circuit Sink Current
Digital Output Capacitance
Analog Supply Current
Digital Output Supply Current
Power Consumption
Power Down Power Consumption
Maximum Clock Frequency
Minimum Clock Frequency
Clock High Time
Clock Low Time
Conversion Latency
Output Delay of CLK to DATA
Data Output Setup Time
Data Output Hold Time
Aperture Delay
Aperture Jitter
= 105 MHz, 50% Duty Cycle, DCS disabled, V
Parameter
Parameter
I
I
V
V
Full Operation
Full Operation (Note 12)
Excludes I
Clock disabled
OUT
OUT
Relative to rising edge of CLK(Note 13)
Relative to DRDY
Relative to DRDY
OUT
OUT
= −0.5 mA , V
= 1.6 mA, V
= 0V
= V
CM
DR
DR
= V
(Note 12)
7
CMO
Conditions
Conditions
DR
DR
, C
= 2.4V
= 2.4V
L
= 5 pF/pin. Typical values are for T
MIN
A
≤
= +3.3V, V
T
A
(Note 10)
(Note 10)
Typical
≤
Typical
5.76
4.5
4.5
0.6
0.1
−10
121
400
T
7.5
10
16
4
4
5
5
MAX
DR
. All other limits apply for
= +2.5V, Internal V
Limits
Limits
A
105
141
466
7.3
3.7
3.8
2.0
0.4
20
7
3
= 25°C. Timing
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Clock Cycles
MHz (max)
MHz (min)
mW (max)
mA (max)
ns (max)
(Limits)
ns (min)
ns (min)
ns (min)
(Limits)
V (max)
V (min)
ps rms
Units
Units
mW
mA
mA
mA
REF
pF
pF
ns
ns
ns
=